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* i965: Allow forcing miptree->array_layout = ALL_SLICES_AT_EACH_LODJordan Justen2014-08-151-1/+2
| | | | | | | | | | | | | gen6 does not support multiple miplevels with separate stencil/hiz. Therefore we need to layout its miptree with no mipmap spacing between the slices of each miplevel. v3: * Use new array_layout enum Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965: Handle miptree creation failure in intel_alloc_texture_storage()Juha-Pekka Heikkila2014-06-261-0/+3
| | | | | | | | Check intel_miptree_create() return value before using it as a pointer. Signed-off-by: Juha-Pekka Heikkila <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965: Adjust map/unmap code for MinLevel/MinLayerChris Forbes2014-04-101-3/+8
| | | | | | | | | | This allows core mesa's TexSubImage paths etc to work correctly with views which have nonzero MinLevel or MinLayer. Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Acked-by: Eric Anholt <[email protected]>
* i965: Add _Format to intel_texobj.Chris Forbes2014-04-101-0/+9
| | | | | | | | | | | This is the actual mesa_format to use. In non-view cases this is always the same as the mt's format. V4: Comment style Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Acked-by: Eric Anholt <[email protected]>
* i965: Add driver hook for TextureViewChris Forbes2014-04-101-0/+41
| | | | | | | | | | | We need to wire the original texture's mt into the view. All the hard work of setting up an appropriate tree of gl_texture_image structures has already been done by core mesa. Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Acked-by: Eric Anholt <[email protected]>
* i965: Drop trailing whitespace from the rest of the driver.Kenneth Graunke2013-12-051-1/+1
| | | | | | | Performed via: $ for file in *; do sed -i 's/ *//g'; done Signed-off-by: Kenneth Graunke <[email protected]>
* i965: Add a real native TexStorage path.Eric Anholt2013-09-301-0/+63
| | | | | | | | | | | | We originally had a path just did the loop and called ctx->Driver.AllocTextureImageBuffer(), which I moved into Mesa core. But we can do better, avoiding incorrect miptree size guesses and later texture validations by just directly allocating the miptree and setting it to all the images. v2: drop debug printf. Reviewed-by: Chad Versace <[email protected]>
* mesa: default DEPTH_TEXTURE_MODE should be RED in the core profileMarek Olšák2013-07-301-1/+1
| | | | | | | Cc: [email protected] Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Move intel_context::intelScreen to brw_context.Kenneth Graunke2013-07-091-2/+1
| | | | | | | Signed-off-by: Kenneth Graunke <[email protected]> Acked-by: Chris Forbes <[email protected]> Acked-by: Paul Berry <[email protected]> Acked-by: Anuj Phogat <[email protected]>
* i965: Pass brw_context to functions rather than intel_context.Kenneth Graunke2013-07-091-5/+6
| | | | | | | | | | | | | | This makes brw_context available in every function that used intel_context. This makes it possible to start migrating fields from intel_context to brw_context. Surprisingly, this actually removes some code, as functions that use OUT_BATCH don't need to declare "intel"; they just use "brw." Signed-off-by: Kenneth Graunke <[email protected]> Acked-by: Chris Forbes <[email protected]> Acked-by: Paul Berry <[email protected]> Acked-by: Anuj Phogat <[email protected]>
* i965: Replace #include "intel_context.h" with brw_context.h.Kenneth Graunke2013-07-091-1/+1
| | | | | | | | | | | brw_context.h includes intel_context.h, but additionally makes the brw_context structure available. Switching this allows us to start using brw_context in more places. Signed-off-by: Kenneth Graunke <[email protected]> Acked-by: Chris Forbes <[email protected]> Acked-by: Paul Berry <[email protected]> Acked-by: Anuj Phogat <[email protected]>
* i965: Move the remaining intel code to the i965 directory.Eric Anholt2013-06-261-1/+189
| | | | | | | | | Now that i915's forked off, they don't need to live in a shared directory. Acked-by: Kenneth Graunke <[email protected]> Acked-by: Chad Versace <[email protected]> Acked-by: Adam Jackson <[email protected]> (and I hear second hand that idr is OK with it, too)
* [965] Move to using shared texture management code.Eric Anholt2007-12-161-316/+1
| | | | | | This removes the delayed texture upload optimization from 965, in exchange for bringing us closer to PBO support. It also disables SGIS_generate_mipmap, which didn't seem to be working before anyway, according to the lodbias demo.
* [965] Replace 965 texture format code with common code.Eric Anholt2007-11-201-0/+1
| | | | | The only functional difference should be that 965 now gets the optimization where textures default to 16bpp when the screen is 16bpp.
* Add Intel i965G/Q DRI driver.Eric Anholt2006-08-091-0/+315
This driver comes from Tungsten Graphics, with a few further modifications by Intel.
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