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path: root/src/mesa/drivers/dri/i965/intel_tex.c
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* meta: Delete the PBO texture upload/download pathJason Ekstrand2017-10-121-63/+0
* i965: drop brw->gen in favor of devinfo->genLionel Landwerlin2017-08-301-1/+2
* i965/tex: Don't pass samples to miptree_create_for_teximageJason Ekstrand2017-08-191-1/+1
* i965/miptree: Rework create flagsJason Ekstrand2017-08-071-2/+2
* i965/miptree: Delete MIPTREE_LAYOUT_TILING_(Y|ANY)Jason Ekstrand2017-08-071-1/+1
* i965/miptree: Check tex image allocation failuresTopi Pohjolainen2017-07-221-0/+2
* i965/miptree: Use num_samples of 1 instead of 0 for single-sampledTopi Pohjolainen2017-07-201-2/+2
* i965: Add a "write" parameter to intel_bufferobj_buffer.Kenneth Graunke2017-07-131-1/+2
* i965: Rename some vague format members of brw_contextChad Versace2017-06-221-1/+1
* i965/drm: Rename drm_bacon_bo to brw_bo.Kenneth Graunke2017-04-101-1/+1
* i965/drm: Use our internal libdrm (drm_bacon) rather than the real one.Kenneth Graunke2017-04-101-1/+1
* i965: Rename intelScreen to screen.Kenneth Graunke2016-09-201-2/+2
* i965: Roll intel_reg.h into brw_defines.hJason Ekstrand2016-08-191-1/+1
* i965/miptree: Enforce that height == 1 for 1-D array texturesJason Ekstrand2016-07-201-0/+2
* i965: Emit SNB write cache flush W/A from brw_emit_pipe_control_flush.Francisco Jerez2016-07-071-8/+0
* i965: intel_texture_barrier reimplementedAlejandro Piñeiro2016-07-011-1/+20
* i965: add ARB_texture_barrier supportIlia Mirkin2015-09-231-0/+9
* i965: Rename MIPTREE_LAYOUT_ALLOC_* -> MIPTREE_LAYOUT_TILING_*.Matt Turner2015-08-061-1/+1
* i965: Push miptree tiling request into flagsBen Widawsky2015-07-161-1/+1
* Revert "i965: Push miptree tiling request into flags"Ben Widawsky2015-07-161-1/+1
* i965: Push miptree tiling request into flagsBen Widawsky2015-07-161-1/+1
* i965: Consolidate certain miptree params to flagsBen Widawsky2015-06-121-5/+3
* i965: replace __FUNCTION__ with __func__Marius Predut2015-04-141-5/+5
* i965: Change intel_miptree_create_for_bo() signatureChad Versace2015-04-131-1/+2
* i965/tex: Don't create read-write textures with non-renderable formatsJason Ekstrand2015-01-281-0/+5
* i965: Implement SetTextureStorageForBufferObjectJason Ekstrand2015-01-221-0/+57
* main: Changed _mesa_alloc_texture_storage to _mesa_AllocTextureStorage_sw.Laura Ekstrand2015-01-081-1/+1
* i965: Fix intel_miptree_map() signature to be more 64-bit safeChad Versace2014-12-221-2/+5
* i965: Allow forcing miptree->array_layout = ALL_SLICES_AT_EACH_LODJordan Justen2014-08-151-1/+2
* i965: Handle miptree creation failure in intel_alloc_texture_storage()Juha-Pekka Heikkila2014-06-261-0/+3
* i965: Adjust map/unmap code for MinLevel/MinLayerChris Forbes2014-04-101-3/+8
* i965: Add _Format to intel_texobj.Chris Forbes2014-04-101-0/+9
* i965: Add driver hook for TextureViewChris Forbes2014-04-101-0/+41
* i965: Drop trailing whitespace from the rest of the driver.Kenneth Graunke2013-12-051-1/+1
* i965: Add a real native TexStorage path.Eric Anholt2013-09-301-0/+63
* mesa: default DEPTH_TEXTURE_MODE should be RED in the core profileMarek Olšák2013-07-301-1/+1
* i965: Move intel_context::intelScreen to brw_context.Kenneth Graunke2013-07-091-2/+1
* i965: Pass brw_context to functions rather than intel_context.Kenneth Graunke2013-07-091-5/+6
* i965: Replace #include "intel_context.h" with brw_context.h.Kenneth Graunke2013-07-091-1/+1
* i965: Move the remaining intel code to the i965 directory.Eric Anholt2013-06-261-1/+189
* [965] Move to using shared texture management code.Eric Anholt2007-12-161-316/+1
* [965] Replace 965 texture format code with common code.Eric Anholt2007-11-201-0/+1
* Add Intel i965G/Q DRI driver.Eric Anholt2006-08-091-0/+315
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