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* i965/chv: Display proper brandingBen Widawsky2016-03-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | "Braswell" is a Cherryview based *thing*. It unfortunately requires extra information to determine its marketing name. Unlike all previous products, and hopefully all future ones, there is no unique 1:1 mapping of PCI device ID to brand string. I put up a fight about adding any complexity to our GL renderer string code for a very long time. However, a wise man made a comment to me that I couldn't argue with: if a user installs Windows on their hardware, the brand string should be the same as what we display in Linux. The Windows driver apparently does this check, so we should too. Note that I did manage to find a good use for this info anyway in the compute shader thread counts. v2: memcpy instead of strncpy, and some minor changes (Matt) Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Jordan Justen <[email protected]
* i965: Query and store GPU properties from kernelBen Widawsky2016-03-111-0/+20
| | | | | | | | | | | | | | | | | Certain products are not uniquely identifiable based on device id alone. The kernel exports an interface to help deal with this. This patch merely introduces the consumer of the interface and makes sure nothing breaks. It is also possible to use these values for programming GPGPU mode, and I plan to do that as well. The interface was introduced in libdrm 2.4.60, which is already required, so it should all be fine. v2: Some minor changes recommended by Matt Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* nir: move to compiler/Emil Velikov2016-01-261-1/+1
| | | | | | Signed-off-by: Emil Velikov <[email protected]> Acked-by: Matt Turner <[email protected]> Acked-by: Jose Fonseca <[email protected]>
* i965: Implement a drirc workaround for broken dual color blending.Kenneth Graunke2016-01-221-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | OpenGL's dual color blending feature was specified so that an implementation could support both multiple render targets (MRT) and dual source blending. Fragment shader outputs specify both "location" (the render target number) and "index" (either color 0 or 1). I believe DirectX only has the notion of "location" - if using dual color blending, location 0 or 1 will specify the operands. If not, then location means the render target index. The two features can't be used together. As such, some applications mistakenly try to use <loc = 0, index = 0> and <loc = 1, index = 0> in a shader used for dual color blending with a single render target, rather than the correct <loc = 0, index = 0> and <loc = 0, index = 1>. In particular, Unigine Heaven 4.0 and Valley 1.0 suffer from this bug. Unigine is aware of the problem, and quickly developed a fix, but has not bothered to change the download link on their website to a working copy in over a year. People were still using the broken version and complaining. We tried working around this by disabling dual color blending, but that apparently hurts performance, and people were once again unhappy. On i965, dual source blending is achieved by using different framebuffer write messages than normal rendering. So, we have to compile different code for the two cases. We're not being pedantic: we actually have to know in order to function. Normally, dual source blending is detectable in the shader: if a shader has an output with index = 1, then it's meant for blending, not MRT. With the broken inputs, they're indistinguishable, so we can only tell by looking at the current GL state. This patch implements a new drirc workaround: export dual_color_blend_by_location=true which makes the i965 driver detect when OpenGL state is configured for dual source blending, and recompile the fragment shader to use the right messages. In that case, we allow either location = 1 or index = 1 to specify the second source for the blending equations. It also re-enables GL_ARB_blend_func_extended for Unigine. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92233 Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Acked-by: Ilia Mirkin <[email protected]>
* i965: Remove unused hw_must_use_separate_stencilBen Widawsky2016-01-131-2/+0
| | | | | | | | | | I spotted this while looking for what needs updating in future platforms. I'm too lazy to go through the git logs, but it was probably missed by Jason when all the brw refactoring happened. Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Start program_string_id from 1, not 0.Kenneth Graunke2015-12-221-0/+1
| | | | | | | | | This way, I can safely use brw_tcs_prog_key::program_string_id == 0 to mean "not filled out because no program exists", which avoids the need for adding an extra boolean to that struct. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/screen: Allow OpenGLES 3.1 for gen8+Jordan Justen2015-12-161-0/+5
| | | | | | | | OpenGLES 3.1 cannot be enabled for gen 7 (Ivy Bridge, Haswell) since they are still missing ARB_stencil_texturing. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Marta Lofstedt <[email protected]>
* Revert "i965: Use MESA_FORMAT_B8G8R8X8_SRGB for RGB visuals"Neil Roberts2015-12-161-6/+7
| | | | | | | | | | | | | | | | | | | | This reverts commit 839793680f99b8387bee9489733d5071c10f3ace. The patch was breaking DRI3 because driGLFormatToImageFormat does not handle MESA_FORMAT_B8G8R8X8_SRGB which ended up making it fail to create the renderbuffer and it would later crash. It's not trivial to add this format because there is no __DRI_IMAGE_FORMAT nor __DRI_IMAGE_FOURCC define for the format either. I'm not sure how difficult adding this would be and whether adding a new format would require some sort of new version for DRI. Seeing as this might take a while to fix I think it makes sense to just revert the patch in the meantime in order to avoid regressing master. It is also not handled in intel_gles3_srgb_workaround and there may be other cases where it breaks. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93388 Acked-by: Jason Ekstrand <[email protected]>
* i965: Use MESA_FORMAT_B8G8R8X8_SRGB for RGB visualsNeil Roberts2015-12-131-7/+6
| | | | | | | | | | | | | | | | | | | | | | | | Previously if the visual didn't have an alpha channel then it would pick a format that is not sRGB-capable. I don't think there's any reason not to always have an sRGB-capable visual. Since 28090b30 there are now visuals advertised without an alpha channel which means that games that don't request alpha bits in the config would end up without an sRGB-capable visual. This was breaking supertuxkart which assumes the winsys buffer is always sRGB-capable. The previous code always used an RGBA format if the visual config itself was marked as sRGB-capable regardless of whether the visual has alpha bits. I think we don't actually advertise any sRGB-capable visuals (but we just use sRGB formats anyway) so it shouldn't make any difference. However this patch also changes it to use RGBX if an sRGB-capable visual is requested without alpha bits for consistency. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92759 Cc: "11.0 11.1" <[email protected]> Cc: Ilia Mirkin <[email protected]> Suggested-by: Ilia Mirkin <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: remove trailing spaces in various filesIago Toral Quiroga2015-11-251-2/+1
| | | | Acked-by: Kenneth Graunke <[email protected]>
* i965: Drop #include of main/glheader.h.Matt Turner2015-11-241-1/+0
| | | | | | It's never used. Reviewed-by: Ian Romanick <[email protected]>
* i965/skl+: Enable support for 16x multisamplingNeil Roberts2015-11-051-1/+4
| | | | Reviewed-by: Ben Widawsky <[email protected]>
* i965: Remove unused devinfo revisionBen Widawsky2015-10-241-3/+11
| | | | | | | | | | | | | | | | I left the function to obtain the revision because it is, and will continue to be useful in the future. I'd rather not have to dig it up every time we need it. Comments left at the implementation to say as much. This was accidentally left here when I moved the early platform support: commit 28ed1e08e8ba98ebd4ff0b56326372f0df9c73ad Author: Ben Widawsky <[email protected]> Date: Fri Aug 7 13:58:37 2015 -0700 i965/skl: Remove early platform support Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Configure bufmgr debug options from intel_screen.cKristian Høgsberg Kristensen2015-10-081-1/+13
| | | | | | | | | | | | | | We need the debug flag parsing and INTEL_DEBUG in the compiler, but we don't want the dependency on bufmgr (libdrm_intel) in there. Move to intel_screen.c. There are now only two lines left in brw_process_intel_debug_variable(), but we keep it in intel_debug.h to avoid having to expose 'debug_control' as a global variable. Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> Signed-off-by: Kristian Høgsberg Kristensen <[email protected]>
* i965: Fix typos in licenseIan Romanick2015-09-101-2/+2
| | | | | | | | | | | | | | | | grep -lr 'sub license' | while read f; do \ sed --in-place -e 's/sub license/sublicense/' $f ;\ done grep -lr 'NON-INFRINGEMENT' | while read f; do \ sed --in-place -e 's/NON-INFRINGEMENT/NONINFRINGEMENT/' $f ;\ done As noted by Matt, both of these changes match the MIT license text found at http://opensource.org/licenses/MIT. Signed-off-by: Ian Romanick <[email protected]> Acked-by: Matt Turner <[email protected]>
* i965: Remove horizontal bars from file header commentsIan Romanick2015-09-101-4/+2
| | | | | | | Why was that ever a thing? Signed-off-by: Ian Romanick <[email protected]> Acked-by: Matt Turner <[email protected]>
* i965: Resolve GCC sign-compare warning.Rhys Kidd2015-08-181-3/+3
| | | | | | | | | | | | | | | | mesa/src/mesa/drivers/dri/i965/intel_screen.c: In function 'intel_screen_make_configs': mesa/src/mesa/drivers/dri/i965/intel_screen.c:1222:22: warning: comparison between signed and unsigned integer expressions [-Wsign-compare] for (int i = 0; i < ARRAY_SIZE(formats); i++) { ^ mesa/src/mesa/drivers/dri/i965/intel_screen.c:1259:22: warning: comparison between signed and unsigned integer expressions [-Wsign-compare] for (int i = 0; i < ARRAY_SIZE(formats); i++) { ^ mesa/src/mesa/drivers/dri/i965/intel_screen.c:1291:22: warning: comparison between signed and unsigned integer expressions [-Wsign-compare] for (int i = 0; i < ARRAY_SIZE(formats); i++) { ^ Signed-off-by: Rhys Kidd <[email protected]> Reviewed-by: Thomas Helland <[email protected]>
* i965: Resolve GCC sign-compare warning.Rhys Kidd2015-08-181-1/+1
| | | | | | | | | | mesa/src/mesa/drivers/dri/i965/intel_screen.c: In function 'aub_dump_bmp': mesa/src/mesa/drivers/dri/i965/intel_screen.c:125:22: warning: comparison between signed and unsigned integer expressions [-Wsign-compare] for (int i = 0; i < fb->_NumColorDrawBuffers; i++) { ^ Signed-off-by: Rhys Kidd <[email protected]> Reviewed-by: Thomas Helland <[email protected]>
* i965: Support importing R8 and GR88 dma_bufsChad Versace2015-07-281-0/+6
| | | | | | | | | | | EGL_EXT_image_dma_buf_import now supports those formats. Tests: - Tested by Piglit ext_image_dma_buf_import-transcode-nv12-as-r8-gr88. - Tested by Peter in Kodi/XBMC to obtain 60fps NV12 transcode at 4K. Tested-by: Peter Frühberger <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* i965: Use updated kernel interface for accurate TIMESTAMP readsChris Wilson2015-07-241-13/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | I was mistaken, I thought we already had fixed this in the kernel a couple of years ago. We had not, and the broken read (the hardware shifts the register output on 64bit kernels, but not on 32bit kernels) is now enshrined into the ABI. I also had the buggy architecture reversed, believing it to be 32bit that had the shifted results. On the basis of those mistakes, I wrote commit c8d3ebaffc0d7d915c1c19d54dba61fd1e57b338 Author: Chris Wilson <[email protected]> Date: Wed Apr 29 13:32:38 2015 +0100 i965: Query whether we have kernel support for the TIMESTAMP register once Now that we do have an extended register read interface for always reporting the full 36bit TIMESTAMP (irrespective of whether the hardware is buggy or not), make use of it and in the process fix my reversed detection of the buggy reads for unpatched kernels. Signed-off-by: Chris Wilson <[email protected]> Cc: Martin Peres <[email protected]> Cc: Kenneth Graunke <[email protected]> Cc: Michał Winiarski <[email protected]> Cc: Daniel Vetter <[email protected]> Tested-and-acked-by: Chris Forbes <[email protected]> Reviewed-by: Daniel Vetter <[email protected]>
* i965: Enable resource streamer for the batchbufferAbdiel Janulgue2015-07-181-0/+14
| | | | | | | | | | | | | | | | | | | | | Check first if the hardware and kernel supports resource streamer. If this is allowed, tell the kernel to enable the resource streamer enable bit on MI_BATCHBUFFER_START by specifying I915_EXEC_RESOURCE_STREAMER execbuffer flags. v2: - Use new I915_PARAM_HAS_RESOURCE_STREAMER ioctl to check if kernel supports RS (Ken). - Add brw_device_info::has_resource_streamer and toggle it for Haswell, Broadwell, Cherryview, Skylake, and Broxton (Ken). v3: - Update I915_PARAM_HAS_RESOURCE_STREAMER to match updated kernel. v4: - Always inspect the getparam.value (Chris Wilson). v5: - Fold redundant devinfo->has_resource_streamer check in context create into init screen. Cc: [email protected] Cc: [email protected] Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Abdiel Janulgue <[email protected]>
* i965: bump libdrm requirement to 2.4.61 and drop in-tree workaroundEmil Velikov2015-07-131-5/+0
| | | | | Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* i965: Query whether we have kernel support for the TIMESTAMP register onceChris Wilson2015-07-081-0/+22
| | | | | | | | | | | | | | | | Move the query for the TIMESTAMP register from context init to the screen, so that it is only queried once for all contexts. On 32bit systems, some old kernels trigger a hw bug resulting in the TIMESTAMP register being shifted and the low 32bits always zero. Detect this by repeating the read a few times and check the register is incrementing every 80ns as expected and not stuck on zero (as would be the case with the buggy kernel/hw.). Signed-off-by: Chris Wilson <[email protected]> Cc: Martin Peres <[email protected]> Reviewed-by: Martin Peres <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Add compiler options to brw_compilerJason Ekstrand2015-06-231-0/+1
| | | | | | | | | | | | | This creates the options at screen cration time and then we just copy them into the context at context creation time. We also move is_scalar to the brw_compiler structure. We also end up manually setting some values that the core would have set by default for us. Fortunately, there are only two non-zero shader compiler option defaults that we aren't overriding anyway so this isn't a big deal. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* i965: Move INTEL_DEBUG variable parsing to screen creation timeJason Ekstrand2015-06-231-0/+2
| | | | | | v2: Do bufmgr set_debug and set_aub_dump at screen time as well. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Store the command parser version number in intel_screenNeil Roberts2015-05-121-0/+7
| | | | | | | | | In order to detect whether the predicate source registers can be used in a later patch we will need to know the version number for the command parser. This patch just adds a member to intel_screen and does an ioctl to get the version. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/sync: Implement DRI2_Fence extensionChad Versace2015-05-071-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This enables EGL_KHR_fence_sync and EGL_KHR_wait_sync. Below is the difference in piglit results, before and after this patch. No regressions and several tests improve from 'skip' to 'pass'. Out of EGL_KHR_fence_sync tests, two of the multithreaded tests skip; all other tests pass. cmdline: piglit run -p gbm -t sync tests/quick.py mesa: master@1ac7db0 piglit: 4069bec hw: Ivybridge | before after ------+------------- pass | 32 46 fail | 0 0 crash | 0 0 skip | 35 21 total | 67 67 v2: - Set fence->signalled = true in brw_fence_has_completed() too. Reviewed-by: Daniel Stone <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Add XRGB8888 format to intel_screen_make_configsBoyan Ding2015-05-051-1/+2
| | | | | | | | | | | | | | Some application, such as drm backend of weston, uses XRGB8888 config as default. i965 doesn't provide this format, but before commit 65c8965d, the drm platform of EGL takes ARGB8888 as XRGB8888. Now that commit 65c8965d makes EGL recognize format correctly so weston won't start because it can't find XRGB8888. Add XRGB8888 format to i965 just as other drivers do. Cc: [email protected] Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89689 Signed-off-by: Boyan Ding <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965: Add a brw_compiler structure and store the register sets in itJason Ekstrand2015-04-221-2/+3
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/device_info: Add a supports_simd16_3src flagJason Ekstrand2015-04-221-1/+25
| | | | | | | | | | This also involves moving revision checking to screen creation time and passing that into brw_get_device_info so that we can get the right device_info for early versions of SKL. Since the only place we used revision was to check for SIMD16 3-src instruction support, it's safe to remove the revision field from brw_context. Reviewed-by: Matt Turner <[email protected]>
* i965: replace __FUNCTION__ with __func__Marius Predut2015-04-141-2/+2
| | | | | | | | Consistently just use C99's __func__ everywhere. No functional changes. Acked-by: Matt Turner <[email protected]> Signed-off-by: Marius Predut <[email protected]>
* egl: add initial EGL_MESA_image_dma_buf_export v2.4Dave Airlie2015-04-011-2/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | At the moment to get an EGL image to a dma-buf file descriptor, you have to use EGL_MESA_drm_image, and then use libdrm to convert this to a file descriptor. This extension just provides an API modelled on EGL_MESA_drm_image, to return a dma-buf file descriptor. v2: update spec for new API proposal add internal queries to get the fourcc back from intel driver. v2.1: add gallium pieces. v2.2: add offsets to spec and API, rename fd->fds, stride->strides in API. rewrite spec a bit more, add some q/a v2.3: add modifiers to query interface and 64-bit type for that (Daniel Stone) specifiy what happens to num fds vs num planes differences. (Chad Versace) v2.4: fix grammar (Daniel Stone) Signed-off-by: Dave Airlie <[email protected]>
* i965: Throttle rendering to an fboChris Wilson2015-03-181-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When rendering to an fbo, even though it may be acting as a winsys frontbuffer or just generally, we never throttle. However, when rendering to an fbo, there is no natural frame boundary. Conventionally we use SwapBuffers and glFinish, but potential callers avoid often glFinish for being too heavy handed (waiting on all outstanding rendering to complete). The kernel provides a soft-throttling option for this case that waits for rendering older than 20ms to be complete (that's a little too lax to be used for swapbuffers, but is here a useful safety net). The remaining choice is then either never to throttle, throttle after every draw call, or at after intermediate user defined point such as glFlush and thus all the implied flushes. This patch opts for the latter as that is the current method used for flushing to front buffers. v2: Defer the throttling from inside the flush to the next intel_prepare_render() and switch non-fbo frontbuffer throttling over to use the same lax method. The issuing being that glFlush()/intel_prepare_read() is just as likely to be called inside a tight loop and not at "frame" boundaries. v3: Rename from need_front_throttle to need_flush_throttle to avoid any ambiguity between front buffer rendering and fbo rendering. (Chad) v4: Whitespace Signed-off-by: Chris Wilson <[email protected]> Cc: Daniel Vetter <[email protected]> Cc: Kenneth Graunke <[email protected]> Cc: Ben Widawsky <[email protected]> Cc: Kristian Høgsberg <[email protected]> Cc: Chad Versace <[email protected]> Cc: Ian Romanick <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965: Remove "disable_derivative_optimization" driconf option.Kenneth Graunke2014-12-021-4/+0
| | | | | | | | | | | | | This was added in September 2013 when we first implemented the fast (but lower quality) derivatives. A quick Google search didn't turn up anyone using or recommending the option, so I suspect no one does. Applications that want to control the quality of their derivatives can use the new GL_ARB_derivative_control extension, or use the glHint mechanism. The driconf option seems superfluous. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/skl: Set max OpenGL version the same as gen7/8Jordan Justen2014-11-031-0/+1
| | | | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965: Delete intel_chipset.h.Kenneth Graunke2014-09-291-1/+0
| | | | | | Unused; it was replaced by include/pci_ids/i965_pci_ids.h long ago. Acked-by: Matt Turner <[email protected]>
* i965/gen6: Enable GL 3.3 and GLSL 3.30Chris Forbes2014-09-201-6/+1
| | | | | | | | | | | | Tested on my snb-gt2: 4 tests skip->pass in spec/EXT_texture_array 51 tests skip->pass in spec.glsl-3.30 4 tests skip->pass in spec/!OpenGL 3.3 No regressions; no skip->fail changes. Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/gen6: enable GLSL 1.50, OpenGL 3.2 and GL_AMD_vertex_shader_layeredSamuel Iglesias Gonsalvez2014-09-191-1/+1
| | | | | | | | | | | | | | | | Geometry shaders was the only thing we needed to enable GLSL 1.50 and OpenGL 3.2 in gen6. v2: Layered clears do not work properly in gen6 with OpenGL 3.2. Kenneth and Jordan realized that for this to work we also need GL_AMD_vertex_shader_layered (which requires OpenGL 3.2, so it could not be enabled before this patch), so we agreed to enable this together with OpenGL 3.2 in this patch. Signed-off-by: Samuel Iglesias Gonsalvez <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965: add support for RGBA dma_buf imports.Gwenole Beauchesne2014-09-161-0/+6
| | | | | | | | | This allows for importing foreign buffers in RGB32 native endian byte order, i.e. DRM_FORMAT_XBGR8888, and DRM_FORMAT_ABGR8888. Signed-off-by: Gwenole Beauchesne <[email protected]> Acked-by: Kenneth Graunke <[email protected]> Cc: "10.3" <[email protected]>
* dri/common: Move __DRI2_RENDERER_PREFFERED_PROFILE handling to ↵Emil Velikov2014-08-151-4/+0
| | | | | | | | | | | | driQueryRendererIntegerCommon Essentially all drivers would like to use to opengl core profile if available, so avoid duplication by moving the code to a common fallback within driQueryRendererIntegerCommon. If a driver uses different approach they can handle it separately. Signed-off-by: Emil Velikov <[email protected]>
* i965: Support the allow_glsl_extension_directive_midshader option.Kenneth Graunke2014-08-101-0/+1
| | | | | | | | | | | This adds support for Marek's new driconf parameter, which avoids totally white rendering in Unigine Valley (which attempts to enable the GL_ARB_sample_shading extension in an illegal place). Signed-off-by: Kenneth Graunke <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=75664 Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* util: Move ralloc to a new src/util directory.Kenneth Graunke2014-08-041-1/+1
| | | | | | | | | | | | | | | | | | For a long time, we've wanted a place to put utility code which isn't directly tied to Mesa or Gallium internals. This patch creates a new src/util directory for exactly that purpose, and builds the contents as libmesautil.la. ralloc seemed like a good first candidate. These days, it's directly used by mesa/main, i965, i915, and r300g, so keeping it in src/glsl didn't make much sense. Signed-off-by: Kenneth Graunke <[email protected]> v2 (Jason Ekstrand): More realloc uses and some scons fixes Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* i965: Use unreachable() instead of unconditional assert().Matt Turner2014-07-011-2/+1
| | | | Reviewed-by: Ian Romanick <[email protected]>
* i965: Rename intel_regions.h to something more appropriate now.Eric Anholt2014-05-011-1/+1
| | | | | | | | We had the EGLimage structure laying around in intel_regions.h, but now it's the only thing left in the file. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965: Drop region usage from DRI2 winsys-allocated buffers.Eric Anholt2014-05-011-13/+17
| | | | | | | v2: Fix bad pointer on unreference (caught by Chad) Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965: Drop a funny assert about mt pitch.Eric Anholt2014-05-011-1/+0
| | | | | | | | | I slipped this in in the region->pitch change from pixels to bytes, but I don't see any reason for it any more -- the libdrm code doesn't appear to divide pitch by a cpp. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965: Drop use of intel_region from miptrees.Eric Anholt2014-05-011-11/+11
| | | | | | | | | | | | Note: region->width/height used to reflect the total_width/height padding of separate stencil, though mt->total_width didn't. region->width/height was being used in EGL images, where the padded value would have been the wrong one, so I converted them to use rb->Width/Height. v2: Drop debug printf that slipped in (caught by Ken) Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965: Replace the region in DRIimage with just a BO pointer and stride.Eric Anholt2014-05-011-69/+68
| | | | | | | | | | | | | Regions aren't refcounted safely for multithreaded applications, and they're not terribly useful wrappers of a BO, so I'm trying to remove them. Even the stride I added here could probably be reduced to use of an existing field in the __DRIimageRec, but I want this to be as mechanical of a change as possible. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965: Drop the global GEM name from regions.Eric Anholt2014-05-011-2/+2
| | | | | | | Once a buffer has been named, drm_intel_bo_flink() is just a getter. Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965: Fix another broken offset-aligned-to-tile test.Eric Anholt2014-05-011-3/+1
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Chad Versace <[email protected]>
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