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* i965: Emit SNB write cache flush W/A from brw_emit_pipe_control_flush.Francisco Jerez2016-07-071-8/+0
| | | | | | | | Shouldn't cause any functional changes at this point, but we have forgotten to apply this workaround several times in the past, make sure it doesn't happen again. Reviewed-by: Alejandro Piñeiro <[email protected]>
* i965: don't use NumLayers for 3D textures.Dave Airlie2016-06-061-1/+1
| | | | | | | | | | | | For 3D textures we shouldn't be using NumLayers, we need to get it from the depth. This fixes: GL45-CTS.geometry_shader.layered_framebuffer.clear_call_support Reviewed-by: Eduardo Lima Mitev <[email protected]> Cc: "12.0" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* i965: Use blorp for all stencil blitsJason Ekstrand2016-05-141-6/+1
| | | | | | | We used to use a meta path because blorp didn't support 16x MSAA. Now it does, so we don't need the meta paths anymore. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Fix brw_render_cache_set_check_flush's PIPE_CONTROLs.Kenneth Graunke2016-03-281-1/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Our driver uses the brw_render_cache mechanism to track buffers we've rendered to and are about to sample from. Previously, we did a single PIPE_CONTROL with the following bits set: - Render Target Flush - Depth Cache Flush - Texture Cache Invalidate - VF Cache Invalidate - Instruction Cache Invalidate - CS Stall This combined both "top of pipe" invalidations and "bottom of pipe" flushes, which isn't how the hardware is intended to be programmed. The "top of pipe" invalidations may happen right away, without any guarantees that rendering using those caches has completed. That rendering may continue altering the caches. The "bottom of pipe" flushes do wait for the rendering to complete. The CS stall also prevents further work from happening until data is flushed out. What we wanted to do was wait for rendering complete, flush the new data out of the render and depth caches, wait, then invalidate any stale data in read-only caches. We can accomplish this by doing the "bottom of pipe" flushes with a CS stall, then the "top of pipe" flushes as a second PIPE_CONTROL. The flushes will wait until the rendering is complete, and the CS stall will prevent the second PIPE_CONTROL with the invalidations from executing until the first is done. Fixes dEQP-GLES3.functional.texture.specification.teximage2d_pbo subtests on Braswell and Skylake. These tests hit the meta PBO texture upload path, which binds the PBO as a texture and samples from it, while rendering to the destination texture. The tests then sample from the texture. For now, we leave Gen4-5 alone. It probably needs work too, but apparently it hasn't even been setting the (G45+) TC invalidation bit at all... v2: Add Sandybridge post-sync non-zero workaround, for safety. Cc: [email protected] Suggested-by: Francisco Jerez <[email protected]> Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* i965: Set a proper _BaseFormat for window system renderbuffers in ES.Kenneth Graunke2016-03-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | intel_alloc_private_renderbuffer_storage did: rb->_BaseFormat = _mesa_base_fbo_format(ctx, internalFormat); Unfortunately, internalFormat was usually an unsized format (such as GL_DEPTH_COMPONENT). In OpenGL ES, _mesa_base_fbo_format() refuses to accept unsized formats, and returns 0 rather than a real base format. This meant that we ended up with a completely bogus rb->_BaseFormat for window system buffers on OpenGL ES. All other renderbuffer allocation functions in intel_fbo.c instead use the mesa_format, and do: rb->_BaseFormat = _mesa_get_format_base_format(...); We can do likewise, using rb->Format. This appears to work just fine. dEQP-GLES3.functional.state_query.fbo.framebuffer_attachment_x_size_initial failed, as it tried to perform a GL_FRAMEBUFFER_ATTACHMENT_DEPTH_SIZE query on the window system depth buffer. That query relies on a proper rb->_BaseFormat being set, so it broke because rb->_BaseFormat was 0 due to the above bug. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94458 Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]>
* i965: Add missing close-parenthesis in error messagesIan Romanick2015-10-261-2/+2
| | | | | | Trivial. Signed-off-by: Ian Romanick <[email protected]>
* i965: Fix is-renderable check in intel_image_target_renderbuffer_storageIan Romanick2015-10-261-5/+1
| | | | | | | | | | | | | | | | | | | | | | | | Previously we could create a renderbuffer with format MESA_FORMAT_R8G8B8A8_UNORM, convert that renderbuffer to an EGLImage, then FAIL to convert the EGLImage back to a renderbuffer because reasons. Just use the same check in intel_image_target_renderbuffer_storage that brw_render_target_supported uses. There are more checks in brw_render_target_supported, but I don't think they are necessary here. A different approach would be to refactor brw_render_target_supported to take rb->Format and rb->NumSamples as parameters (instead of a gl_renderbuffer) and use the new function here. Fixes: ES2-CTS.gtf.GL2ExtensionTests.egl_image.egl_image Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> Tested-by: Tapani Pälli <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92476 Cc: "10.3 10.4 10.5 10.6 11.0" <[email protected]>
* i965: Don't override NewFramebuffer just to call _mesa_new_framebufferIan Romanick2015-10-061-14/+0
| | | | | Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* i965: Rename intel_miptree_get_dimensions_for_image()Anuj Phogat2015-09-281-1/+1
| | | | | | | | | | | This function isn't specific to miptrees. So, drop the "miptree" from function name. V3: Add a comment explaining how the 1D Array texture height and depth is interpreted by Intel hardware. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965: Silence unused parameter warnings in intel_fbo.cIan Romanick2015-09-101-3/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | intel_fbo.c: In function 'intel_alloc_window_storage': intel_fbo.c:415:48: warning: unused parameter 'ctx' [-Wunused-parameter] intel_alloc_window_storage(struct gl_context * ctx, struct gl_renderbuffer *rb, ^ intel_fbo.c: In function 'intel_nop_alloc_storage': intel_fbo.c:428:74: warning: unused parameter 'rb' [-Wunused-parameter] intel_nop_alloc_storage(struct gl_context * ctx, struct gl_renderbuffer *rb, ^ intel_fbo.c:429:32: warning: unused parameter 'internalFormat' [-Wunused-parameter] GLenum internalFormat, GLuint width, GLuint height) ^ intel_fbo.c:429:55: warning: unused parameter 'width' [-Wunused-parameter] GLenum internalFormat, GLuint width, GLuint height) ^ intel_fbo.c:429:69: warning: unused parameter 'height' [-Wunused-parameter] GLenum internalFormat, GLuint width, GLuint height) ^ intel_fbo.c: In function 'intel_blit_framebuffer_with_blitter': intel_fbo.c:790:61: warning: unused parameter 'filter' [-Wunused-parameter] GLbitfield mask, GLenum filter) ^ Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965: Fix typos in licenseIan Romanick2015-09-101-2/+2
| | | | | | | | | | | | | | | | grep -lr 'sub license' | while read f; do \ sed --in-place -e 's/sub license/sublicense/' $f ;\ done grep -lr 'NON-INFRINGEMENT' | while read f; do \ sed --in-place -e 's/NON-INFRINGEMENT/NONINFRINGEMENT/' $f ;\ done As noted by Matt, both of these changes match the MIT license text found at http://opensource.org/licenses/MIT. Signed-off-by: Ian Romanick <[email protected]> Acked-by: Matt Turner <[email protected]>
* i965: Remove horizontal bars from file header commentsIan Romanick2015-09-101-5/+2
| | | | | | | Why was that ever a thing? Signed-off-by: Ian Romanick <[email protected]> Acked-by: Matt Turner <[email protected]>
* i965: Resolve GCC sign-compare warning.Rhys Kidd2015-08-181-1/+1
| | | | | | | | | | mesa/src/mesa/drivers/dri/i965/intel_fbo.c: In function 'intel_validate_framebuffer': mesa/src/mesa/drivers/dri/i965/intel_fbo.c:734:18: warning: comparison between signed and unsigned integer expressions [-Wsign-compare] for (i = 0; i < ARRAY_SIZE(fb->Attachment); i++) { ^ Signed-off-by: Rhys Kidd <[email protected]> Reviewed-by: Thomas Helland <[email protected]>
* i965: Resolve GCC sign-compare warning.Rhys Kidd2015-08-181-1/+1
| | | | | | | | | | | | mesa/src/mesa/drivers/dri/i965/intel_fbo.c: In function 'intel_blit_framebuffer_with_blitter': mesa/src/mesa/drivers/dri/i965/intel_fbo.c:836:21: warning: comparison between signed and unsigned integer expressions [-Wsign-compare] for (i = 0; i < drawFb->_NumColorDrawBuffers; i++) { ^ V2 (Thomas Helland): -Use unsigned instead of GLuint (trivial) Signed-off-by: Rhys Kidd <[email protected]> Reviewed-by: Thomas Helland <[email protected]>
* i965: Rename MIPTREE_LAYOUT_ALLOC_* -> MIPTREE_LAYOUT_TILING_*.Matt Turner2015-08-061-1/+1
| | | | | | | | | Ben suggested that I rename MIPTREE_LAYOUT_ALLOC_ANY_TILED since it needed to include no tiling at all, but the name MIPTREE_LAYOUT_ALLOC_ANY is pretty nondescriptive. We can avoid confusion by replacing "ALLOC" with "TILING" in the identifiers. Reviewed-by: Ben Widawsky <[email protected]>
* mesa: Rename _mesa_lookup_enum_by_nr() to _mesa_enum_to_string().Kenneth Graunke2015-07-201-1/+1
| | | | | | | Generated by sed; no manual changes. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* i965: Push miptree tiling request into flagsBen Widawsky2015-07-161-2/+4
| | | | | | | | | | | | | | | | | | | | | With the last few patches a way was provided to influence lower layer miptree layout and allocation decisions via flags (replacing bools). For simplicity, I chose not to touch the tiling requests because the change was slightly less mechanical than replacing the bools. The goal is to organize the code so we can continue to add new parameters and tiling types while minimizing risk to the existing code, and not having to constantly add new function parameters. v2: Rebased on Anuj's recent Yf/Ys changes Fix non-msrt MCS allocation (was only happening in gen8 case before) v3: small fix in assertion requested by Chad v4: Use parens to get the order right from v3. Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* Revert "i965: Push miptree tiling request into flags"Ben Widawsky2015-07-161-4/+2
| | | | This reverts commit 51e8d549e110f86cb7107cf712843aebd956fb9a.
* i965: Push miptree tiling request into flagsBen Widawsky2015-07-161-2/+4
| | | | | | | | | | | | | | | | | | | | | With the last few patches a way was provided to influence lower layer miptree layout and allocation decisions via flags (replacing bools). For simplicity, I chose not to touch the tiling requests because the change was slightly less mechanical than replacing the bools. The goal is to organize the code so we can continue to add new parameters and tiling types while minimizing risk to the existing code, and not having to constantly add new function parameters. v2: Rebased on Anuj's recent Yf/Ys changes Fix non-msrt MCS allocation (was only happening in gen8 case before) v3: small fix in assertion requested by Chad Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Jordan Justen <[email protected]> (v2) Reviewed-by: Anuj Phogat <[email protected]> (v2) Reviewed-by: Chad Versace <[email protected]> (v2)
* i965: Don't use GCC extension for ?: with only two operands.Kenneth Graunke2015-06-291-3/+5
| | | | | | | | | | | | | | | | | | | From the "apparently I don't know C" files...GCC apparently supports: x ?: y which is equivalent to x ? x : y except that it doesn't cause side-effects to occur twice. See: https://gcc.gnu.org/onlinedocs/gcc/Conditionals.html#Conditionals This was confusing and looked like a typo. It doesn't really buy us anything, so just write the obvious code in normal C. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* i965: Rename intel_emit* to reflect their new location in brw_pipe_controlChris Wilson2015-06-241-1/+1
| | | | | Signed-off-by: Chris Wilson <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Consolidate certain miptree params to flagsBen Widawsky2015-06-121-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I think pretty much everyone agrees that having more than a single bool as a function argument is bordering on a bad idea. What sucks about the current code is in several instances it's necessary to propagate these boolean selections down to lower layers of the code. This requires plumbing (mechanical, but still churn) pretty much all of the miptree functions each time. By introducing the flags paramater, it is possible to add miptree constraints very easily. The use of this, as is already the case, is sometimes we have some information at the time we create the miptree that needs to be known all the way at the lowest levels of the create/allocation, disable_aux_buffers is currently one such example. There will be another example coming up in a few patches. v2: Tab fix. (Ben) Long line fixes (Topi) Use anonymous enum instead of #define for layout flags (Chad) Use 'X != 0' instead of !!X (everyone except Chad) v3: Some non-trivial conflict resolution on top of Anuj's patches. Signed-off-by: Ben Widawsky <[email protected]> Cc: "Pohjolainen, Topi" <[email protected]> Reviewed-by: Chad Versace <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965: replace __FUNCTION__ with __func__Marius Predut2015-04-141-4/+4
| | | | | | | | Consistently just use C99's __func__ everywhere. No functional changes. Acked-by: Matt Turner <[email protected]> Signed-off-by: Marius Predut <[email protected]>
* i965: Lift some restrictions on dma_buf EGLImagesChad Versace2015-04-131-7/+0
| | | | | | | | | | | | | | | | | | | | | Allow glEGLImageTargetRenderbufferStorageOES and glEGLImageTargetTexture2DOES for dma_buf EGLImages if the image is a single RGBA8 unorm plane. This is safe, despite fast color clears, because i965 disables allocation of auxiliary buffers for EGLImages. Chrome OS needs this, because its compositor uses dma_buf EGLImages for its scanout buffers. Testing: - Tested on Ivybridge Chromebook Pixel with WebGL Aquarium and YouTube. - No Piglit regressions on Broadwell with `piglit run -p gbm tests/quick.py`, with my Piglit patches that update the EGL_EXT_image_dma_buf_import tests. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Tapani Pälli <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Disable aux buffers for EGLImage-backed miptreesChad Versace2015-04-131-1/+7
| | | | | | | | | | | | | | | | | | | | EGL does not yet have extensions to manage the flushing and invalidating of driver-internal aux buffers. So we must disable aux buffers of dma_buf-backed EGLImages in order to safely render into them. This patch is obviously needed for renderbufers. It's also needed for textures because the user can attach the texture to a framebuffer and because the driver sometimes renders to textures for internal reasons. Testing: - Tested on Ivybridge Chromebook Pixel with WebGL Aquarium and YouTube. - No Piglit regressions on Broadwell with `piglit run -p gbm tests/quick.py`. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Tapani Pälli <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Change intel_miptree_create_for_bo() signatureChad Versace2015-04-131-1/+2
| | | | | | | | | | | Add parameter 'bool disable_aux_buffers'. This is a refactor patch. The patch changes no behavior because the new parameter is false in every call. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Tapani Pälli <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Refactor brw_is_hiz_depth_format()Chad Versace2015-04-131-2/+2
| | | | | | | | | | | | | | | | | | | | | Every caller of this function uses it to determine if the current miptree needs a hiz buffer to be allocated. Strangely, the function doesn't take a miptree argument. So, this function effectively decides if and when a miptree's hiz buffer gets allocated without inspecting the miptree itself. Luckily, the driver behaves correctly despite the brw_is_hiz_depth_format's quirk. I will soon make some changes to the miptree that will require inspecting the miptree to determine if it needs a hiz buffer. So this patch renames brw_is_hiz_depth_format -> intel_miptree_wants_hiz_buffer and gives it a miptree parameter. This patch shouldn't change any behavior. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Tapani Pälli <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/hiz: Start to separate miptree out from hiz buffersJordan Justen2015-03-091-2/+2
| | | | | | | | | | | | | | | | | | | | | | | Today we allocate a miptree's for the hiz buffer. We needed this in the past because we would point the hardware at offsets of the hiz buffer. Since the hiz format is not documented, this is not a good idea. Since moving to support layered rendering on Gen7+, we no longer point at an offset into the buffer on Gen7+. Therefore, to support hiz on Gen7+, we don't need a full miptree structure allocated. This patch starts to create a new auxiliary buffer structure (intel_miptree_aux_buffer) that can be a more simplistic miptree side-band buffer associated with a miptree. (For example, to serve the needs of the hiz buffer.) Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ben Widawsky <[email protected]>
* i965: Split Gen4-5 BlitFramebuffer code; prefer BLT over Meta.Kenneth Graunke2015-03-051-1/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | A while back I switched intel_blit_framebuffer to prefer Meta over the BLT. This meant that Gen8 platforms would start using the 3D engine for blits, just like we do on Gen6-7.5. However, I hadn't considered Gen4-5 when making that change. The BLT engine appears to be substantially faster on 965GM than using Meta to drive the 3D engine. This isn't too surprising: original Gen4 doesn't support tile offsets (that came on G45), and the level/layer fields don't work for cubemap rendering, so for inconvenient miplevel alignments, we end up blitting or copying data to/from temporaries in order to render to it. We may as well just use the blitter. I chose to use the BLT on Gen4-5 because they use the same ring for both 3D and BLT; Gen6+ splits it out. Fixes regressions on 965GM due to botched tile offset code (we should fix those properly as well, but they're longstanding bugs - for now, put things back to the status quo). Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89430 Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Cc: "10.5" <[email protected]>
* intel: fix EGLImage renderbuffer _BaseFormatFrank Henigman2015-03-031-1/+1
| | | | | | | | | | Correctly set _BaseFormat field when creating a gl_renderbuffer with EGLImage storage. Change-Id: I8c9f7302d18b617f54fa68304d8ffee087ed8a77 Signed-off-by: Frank Henigman <[email protected]> Reviewed-by: Stéphane Marchesin <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965: replace Elements() with ARRAY_SIZE()Brian Paul2015-03-021-1/+1
| | | | Acked-by: Ilia Mirkin <[email protected]>
* mesa: Use assert() instead of ASSERT wrapper.Matt Turner2015-02-231-2/+2
| | | | Acked-by: Eric Anholt <[email protected]>
* i965: Prefer Meta over the BLT for BlitFramebuffer.Kenneth Graunke2015-02-171-7/+7
| | | | | | | | | | | | | | | | | There's some debate about whether we should use Meta or BLORP, but either should run circles around the BLT engine. In particular, this means that Gen8+ will use the 3D engine for blits, like we do on Gen6-7. Improves performance in "copypixrate -blit -back" (from Mesa demos) by 232.037% +/- 3.15795% (n=10) on Broadwell GT3e. v2: Rebase on Laura's changes. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Cc: "10.5" <[email protected]>
* DD: Refactor BlitFramebuffer.Laura Ekstrand2015-02-021-9/+11
| | | | | | | | | In preparation for glBlitNamedFramebuffer, the DD table function BlitFramebuffer needs to accept two arbitrary framebuffer objects rather than assuming ctx->ReadBuffer and ctx->DrawBuffer. Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* i965/mipmap_tree: Add a depth parameter to create_for_boJason Ekstrand2015-01-221-0/+1
| | | | Reviewed-by: Neil Roberts <[email protected]>
* util/hash_set: Rework the API to know about hashingJason Ekstrand2015-01-151-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | Previously, the set API required the user to do all of the hashing of keys as it passed them in. Since the hashing function is intrinsically tied to the comparison function, it makes sense for the hash set to know about it. Also, it makes for a somewhat clumsy API as the user is constantly calling hashing functions many of which have long names. This is especially bad when the standard call looks something like _mesa_set_add(ht, _mesa_pointer_hash(key), key); In the above case, there is no reason why the hash set shouldn't do the hashing for you. We leave the option for you to do your own hashing if it's more efficient, but it's no longer needed. Also, if you do do your own hashing, the hash set will assert that your hash matches what it expects out of the hashing function. This should make it harder to mess up your hashing. This is analygous to 94303a0750 where we did this for hash_table Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* util: Move main/set to util/hash_setJason Ekstrand2015-01-151-1/+1
| | | | | Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Fix intel_miptree_map() signature to be more 64-bit safeChad Versace2014-12-221-2/+2
| | | | | | | | | | | | | | | | | This patch should diminish the likelihood of pointer arithmetic overflow bugs, like the one fixed by b69c7c5dac. Change the type of parameter 'out_stride' from int to ptrdiff_t. The logic is that if you call intel_miptree_map() and use the value of 'out_stride', then you must be doing pointer arithmetic on 'out_ptr'. Using ptrdiff_t instead of int should make a little bit harder to hit overflow bugs. As a side-effect, some function-scope variables needed to be retyped to avoid compilation errors. Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* mesa: Add a source parameter to _mesa_gl_debug.Matt Turner2014-12-051-0/+1
| | | | | Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965: Allow forcing miptree->array_layout = ALL_SLICES_AT_EACH_LODJordan Justen2014-08-151-1/+2
| | | | | | | | | | | | | gen6 does not support multiple miplevels with separate stencil/hiz. Therefore we need to layout its miptree with no mipmap spacing between the slices of each miplevel. v3: * Use new array_layout enum Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965/gen6 fbo: make unmatched depth/stencil configs return unsupportedJordan Justen2014-08-151-3/+3
| | | | | | | | (f3c886b for gen6) Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* util: Move the open-addressing linear-probing hash_table to src/util.Kenneth Graunke2014-08-041-1/+1
| | | | | | | | | | | | | | | | | This hash table is used in core Mesa, the GLSL compiler, and the i965 driver, which makes it a good candidate for the new src/util module. It's much faster than program/hash_table.[ch] (see commit 6991c2922f5 for data), and José's u_hash_table.c has a comment saying Gallium should probably consider switching to a linear probing hash table at some point. So this seems like the best candidate for a shared data structure. Signed-off-by: Kenneth Graunke <[email protected]> v2 (Jason Ekstrand): Pick up another hash_table use and patch up scons Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* meta: Split _swrast_BlitFramebuffer out of the meta blit path.Kenneth Graunke2014-05-191-4/+10
| | | | | | | | | | | | | | | | | | Separating the software fallbacks from the rest of the meta path (which is usually hardware accelerated) gives callers better control over their blitting options. For example, i965 might want to try meta blit, hardware blits, then swrast as a last resort. Splitting it makes that possible. This updates all callers to maintain the existing behavior (even in the few cases where it isn't desirable behavior - later patches can change that). Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Chris Forbes <[email protected]> Cc: "10.2" <[email protected]>
* i965/fbo: Only try stencil meta blits on gen >= 8Topi Pohjolainen2014-05-191-2/+4
| | | | | | | | | I don't have an ILK at hand but the fix should be trivial. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78872 Cc: "10.2" <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-and-tested-by: Kenneth Graunke <[email protected]>
* i965/fb: Use meta path for stencil blitsTopi Pohjolainen2014-05-151-0/+9
| | | | | | | | | This is effective only on gen8 for now as previous generations still go through blorp. Cc: "10.2" <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Move has_hiz from the slice to the level.Eric Anholt2014-05-121-1/+1
| | | | | | | | The value depends only on the level, so no need to store the bool per slice. Shrinks intel_mipmap_slice from 24 bytes to 16, while slotting into an existing hole in intel_mipmap_level. Reviewed-by: Chad Versace <[email protected]>
* i965: Fix typo in assert messageChris Forbes2014-05-091-1/+1
| | | | Signed-off-by: Chris Forbes <[email protected]>
* i965: Rename intel_regions.h to something more appropriate now.Eric Anholt2014-05-011-1/+1
| | | | | | | | We had the EGLimage structure laying around in intel_regions.h, but now it's the only thing left in the file. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965: Replace the region in DRIimage with just a BO pointer and stride.Eric Anholt2014-05-011-6/+6
| | | | | | | | | | | | | Regions aren't refcounted safely for multithreaded applications, and they're not terribly useful wrappers of a BO, so I'm trying to remove them. Even the stride I added here could probably be reduced to use of an existing field in the __DRIimageRec, but I want this to be as mechanical of a change as possible. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965: Drop the tiling argument to intel_miptree_create_for_bo.Eric Anholt2014-05-011-2/+1
| | | | | | | | | The drm function to get the tiling is just a getter storing the two pointers, so we don't need to go out of our way to avoid it. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Chad Versace <[email protected]>
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