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* i965: Fix typos in licenseIan Romanick2015-09-101-2/+2
| | | | | | | | | | | | | | | | grep -lr 'sub license' | while read f; do \ sed --in-place -e 's/sub license/sublicense/' $f ;\ done grep -lr 'NON-INFRINGEMENT' | while read f; do \ sed --in-place -e 's/NON-INFRINGEMENT/NONINFRINGEMENT/' $f ;\ done As noted by Matt, both of these changes match the MIT license text found at http://opensource.org/licenses/MIT. Signed-off-by: Ian Romanick <[email protected]> Acked-by: Matt Turner <[email protected]>
* i965: Remove horizontal bars from file header commentsIan Romanick2015-09-101-5/+2
| | | | | | | Why was that ever a thing? Signed-off-by: Ian Romanick <[email protected]> Acked-by: Matt Turner <[email protected]>
* i965: Prevent coordinate overflow in intel_emit_linear_blitChris Wilson2015-09-011-38/+34
| | | | | | | | | | | | | | | | | | | | | | | | | Fixes regression from commit 8c17d53823c77ac1c56b0548e4e54f69a33285f1 Author: Kenneth Graunke <[email protected]> Date: Wed Apr 15 03:04:33 2015 -0700 i965: Make intel_emit_linear_blit handle Gen8+ alignment restrictions. which adjusted the coordinates to be relative to the nearest cacheline. However, this then offsets the coordinates by up to 63 and this may then cause them to overflow the BLT limits. For the well aligned large transfer case, we can use 32bpp pixels and so reduce the coordinates by 4 (versus the current 8bpp pixels). We also have to be more careful doing the last line just in case it may exceed the coordinate limit. Reported-and-tested-by: [email protected] Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90734 Signed-off-by: Chris Wilson <[email protected]> Cc: Kenneth Graunke <[email protected]> Cc: Ian Romanick <[email protected]> Cc: Anuj Phogat <[email protected]> Cc: [email protected] Reviewed-by: Anuj Phogat <[email protected]>
* Delete duplicate function is_power_of_two() and use _mesa_is_pow_two()Anuj Phogat2015-07-291-4/+4
| | | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* i965: Optimize batchbuffer macros.Matt Turner2015-07-151-9/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | Previously OUT_BATCH was just a macro around an inline function which does brw->batch.map[brw->batch.used++] = dword; When making consecutive calls to intel_batchbuffer_emit_dword() the compiler isn't able to recognize that we're writing consecutive memory locations or that it doesn't need to write batch.used back to memory each time. We can avoid both of these problems by making a local pointer to the next location in the batch in BEGIN_BATCH(). Cuts 18k from the .text size. text data bss dec hex filename 4946956 195152 26192 5168300 4edcac i965_dri.so before 4928956 195152 26192 5150300 4e965c i965_dri.so after This series (including commit c0433948) improves performance of Synmark OglBatch7 by 8.01389% +/- 0.63922% (n=83) on Ivybridge. Reviewed-by: Chris Wilson <[email protected]>
* i965/skl: Extract the blit command setup in to a helperAnuj Phogat2015-06-291-32/+61
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Ben Widawsky <[email protected]>
* i965/gen9: Add XY_FAST_COPY_BLT support to intelEmitCopyBlit()Anuj Phogat2015-06-291-50/+254
| | | | | | | | | | | | | | | | | | This patch enables using XY_FAST_COPY_BLT only for Yf/Ys tiled buffers. It can be later turned on for other tiling patterns (X,Y) too. V3: Flush in between sequential fast copy blits. Fix src/dst alignment requirements. Make can_fast_copy_blit() helper. Use ffs(), is_power_of_two() Move overlap computation inside intel_miptree_blit(). V4: Use _mesa_regions_overlap() function. Add check for src_buffer == dst_buffer. Simplify horizontal and vertical alignment computations. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Ben Widawsky <[email protected]>
* i965: Rename intel_emit* to reflect their new location in brw_pipe_controlChris Wilson2015-06-241-3/+3
| | | | | Signed-off-by: Chris Wilson <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Remove break after returnAnuj Phogat2015-06-151-3/+0
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* i965: Export format comparison for blitting between miptreesChris Wilson2015-06-081-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | Since the introduction of commit 536003c11e4cb1172c540932ce3cce06f03bf44e Author: Boyan Ding <[email protected]> Date: Wed Mar 25 19:36:54 2015 +0800 i965: Add XRGB8888 format to intel_screen_make_configs winsys buffers no longer have an alpha channel. This causes _mesa_format_matches_format_and_type() to reject previously working BGRA uploads from using the BLT fast path. Instead of using the generic routine for matching formats exactly, export the slightly more relaxed check from intel_miptree_blit() which importantly allows the blitter routine to apply a small number of format conversions. References: https://bugs.freedesktop.org/show_bug.cgi?id=90839 Signed-off-by: Chris Wilson <[email protected]> Cc: Jason Ekstrand <[email protected]> Cc: Alexander Monakov <[email protected]> Cc: Kristian Høgsberg <[email protected]> Cc: Kenneth Graunke <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Cc: [email protected]
* i915: Blit RGBX<->RGBA drawpixelsChris Wilson2015-06-081-7/+29
| | | | | | | | | | | | | | | | | | | | The blitter already has code to accommodate filling in the alpha channel for BGRX destination formats, so expand this to also allow filling the alpha channgel in RGBX formats. More importantly for the next patch is moving the test into its own function for the purpose of exporting the check to the callers. v2: Fix alpha expansion as spotted by Alexander with the fix suggested by Kenneth Signed-off-by: Chris Wilson <[email protected]> Cc: Jason Ekstrand <[email protected]> Cc: Alexander Monakov <[email protected]> Cc: Kristian Høgsberg <[email protected]> Cc: Kenneth Graunke <[email protected]> Reviewed-by Kenneth Graunke <[email protected]> Cc: [email protected]
* i965: Fix HW blitter pitch limitsChris Wilson2015-06-081-5/+14
| | | | | | | | | | | | | | The BLT pitch is specified in bytes for linear surfaces and in dwords for tiled surfaces. In both cases the programmable limit is 32,767, so adjust the check to compensate for the effect of tiling. v2: Tweak whitespace for functions (Kenneth) Signed-off-by: Chris Wilson <[email protected]> Cc: Kristian Høgsberg <[email protected]> Cc: Kenneth Graunke <[email protected]> Reviewed-by Kenneth Graunke <[email protected]> Cc: [email protected]
* i965: Disallow linear blits that are not cacheline aligned.Kenneth Graunke2015-04-231-8/+19
| | | | | | | | | | | | | | | The BLT engine on Gen8+ requires linear surfaces to be cacheline aligned. This restriction was added as part of converting the BLT to use 48-bit addressing. The main user, intel_emit_linear_blit, now handles this properly. But we might also have linear miptrees; just refuse to blit those. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88521 Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> Cc: [email protected]
* i965: Make intel_emit_linear_blit handle Gen8+ alignment restrictions.Kenneth Graunke2015-04-231-8/+14
| | | | | | | | | | | | | | | | | | | | The BLT engine on Gen8+ requires linear surfaces to be cacheline aligned. This restriction was added as part of converting the BLT to use 48-bit addressing. intel_emit_linear_blit needs to handle blits that are not cacheline aligned, as we use it for arbitrary glBufferSubData calls and subrange mappings. Since intel_emit_linear_blit uses 1 byte per pixel, we can use the src/dst pixel X offset field to represent the unaligned portion, and subtract that from the address so it's cacheline aligned. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88521 Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> Cc: [email protected]
* i965: replace __FUNCTION__ with __func__Marius Predut2015-04-141-4/+4
| | | | | | | | Consistently just use C99's __func__ everywhere. No functional changes. Acked-by: Matt Turner <[email protected]> Signed-off-by: Marius Predut <[email protected]>
* i965: Add more stringent blitter assertionsBen Widawsky2015-02-071-0/+3
| | | | | | | | | | | | Blits to or from a y-tiled surface must always be a multiple of the tile size. From page 16 of the HSW PRM (https://01.org/linuxgraphics/sites/default/files/documentation/intel-gfx-prm-osrc-hsw-memory-views.pdf#16) "The pitch of a tiled enclosing region must be an integral number of tile widths" Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Consolidate some of the intel_blit logicBen Widawsky2015-02-071-20/+8
| | | | | | | | | | | An upcoming patch is going to introduce some code here, and having this code organized as the patch does makes it a bit easier to read later. There should be no functional change here. Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Require pixel alignment for GPU copy blitCody Northrop2014-12-161-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | The blitter will start at a pixel's natural alignment. For PBOs, if the provided offset if not aligned, bits will get dropped. This change adds offset alignment check for src and dst, kicking back if the requirements are not met. The change is based on following verbiage from BSPEC: Color pixel sizes supported are 8, 16, and 32 bits per pixel (bpp). All pixels are naturally aligned. Found in the following locations: page 35 of intel-gfx-prm-osrc-hsw-blitter.pdf page 29 of ivb_ihd_os_vol1_part4.pdf page 29 of snb_ihd_os_vol1_part5.pdf This behavior was observed with Steam Big Picture rendering incorrect icon colors. The fix has been tested on Ubuntu and SteamOS on Haswell. Signed-off-by: Cody Northrop <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83908 Reviewed-by: Neil Roberts <[email protected]>
* i965/gen8: Check correct number of blitter dwordsBen Widawsky2014-12-111-6/+6
| | | | | | | The odds of having this patch make a difference on Gen8+ are probably very low. Signed-off-by: Ben Widawsky <[email protected]> Reviewed-but-not-tested-by: Jason Ekstrand <[email protected]>
* i965: Use unreachable() instead of unconditional assert().Matt Turner2014-07-011-2/+1
| | | | Reviewed-by: Ian Romanick <[email protected]>
* i965: Delete the intel_regions.c code.Eric Anholt2014-05-011-1/+0
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965: Drop use of intel_region from miptrees.Eric Anholt2014-05-011-18/+17
| | | | | | | | | | | | Note: region->width/height used to reflect the total_width/height padding of separate stencil, though mt->total_width didn't. region->width/height was being used in EGL images, where the padded value would have been the wrong one, so I converted them to use rb->Width/Height. v2: Drop debug printf that slipped in (caught by Ken) Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965: Fix the region's pitch condition to use blitterAnuj Phogat2014-02-261-3/+3
| | | | | | | | | intelEmitCopyBlit uses a signed 16-bit integer to represent buffer pitch, so it can only handle buffer pitches < 32k. Cc: [email protected] Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965: Don't forget to subtract mt->first_level in minify calls.Kenneth Graunke2014-02-261-2/+2
| | | | | | | | | | | This fixes fbo-clear-formats GL_ARB_depth_texture on Ironlake, which regressed since commit f128bcc7c293013f4b44e4b661638333de0077c2 ("i965: Drop mt->levels[].width/height.") intel_miptree_copy_slice was calling minify(.., 7) on a 2x2 texture with mt->first_level == 7. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=75292 Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Don't try to use the hardware blitter for multisampled miptrees.Kenneth Graunke2014-02-231-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | The blitter is completely ignorant of MSAA buffer layouts, so any attempt to use BLT paths with MSAA buffers is likely to break spectacularly. In most cases, BLORP handles MSAA blits, so we never hit this bug. Until recently, it also wasn't worth fixing, since Meta couldn't handle MSAA either, so there was nothing to fall back to. But now there is. +143 piglit tests on Broadwell (which doesn't have BLORP support). Surprisingly, three also start failing. Since non-IMS MSAA buffers store samples in successive array slices, using the blitter ought to access sample 0 and ignore the rest, which is apparently good enough for a few not-very-picky Piglit tests. Presumably the meta replacement code is still broken. No Piglit changes on Ivybridge. v2: Move the early return to the top of the function (suggested by Paul). Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965: Drop mt->levels[].width/height.Eric Anholt2014-02-181-2/+2
| | | | | | | | | | | | It often confused people because it was unclear on whether it was the physical or logical, and people needed the other one as well. We can recompute it trivially using the minify() macro, clarifying which value is being used and making getting the other value obvious. v2: Fix a pasteo in intel_blit.c's dst flip. Reviewed-by: Chris Forbes <[email protected]> (v1) Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: Rename 4 color component unsigned byte MESA_FORMATsMark Mueller2014-01-271-6/+6
| | | | | | | | | | | | | Change all 4 color component unsigned byte formats to meet spec for P Type formats: s/MESA_FORMAT_RGBA8888\b/MESA_FORMAT_A8B8G8R8_UNORM/g s/MESA_FORMAT_RGBA8888_REV\b/MESA_FORMAT_R8G8B8A8_UNORM/g s/MESA_FORMAT_ARGB8888\b/MESA_FORMAT_B8G8R8A8_UNORM/g s/MESA_FORMAT_ARGB8888_REV\b/MESA_FORMAT_A8R8G8B8_UNORM/g s/MESA_FORMAT_RGBX8888\b/MESA_FORMAT_X8B8G8R8_UNORM/g s/MESA_FORMAT_RGBX8888_REV\b/MESA_FORMAT_R8G8B8X8_UNORM/g s/MESA_FORMAT_XRGB8888\b/MESA_FORMAT_B8G8R8X8_UNORM/g s/MESA_FORMAT_XRGB8888_REV\b/MESA_FORMAT_X8R8G8B8_UNORM/g
* mesa: change gl_format to mesa_formatMark Mueller2014-01-271-2/+2
| | | | s/\bgl_format\b/mesa_format/g. Use better name for Mesa Formats enum
* i965: Update blitter code for 48-bit addresses.Kenneth Graunke2014-01-201-16/+48
| | | | | | | v2: Rebase on Eric's SET_FIELD changes. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> [v1]
* s/Tungsten Graphics/VMware/José Fonseca2014-01-171-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tungsten Graphics Inc. was acquired by VMware Inc. in 2008. Leaving the old copyright name is creating unnecessary confusion, hence this change. This was the sed script I used: $ cat tg2vmw.sed # Run as: # # git reset --hard HEAD && find include scons src -type f -not -name 'sed*' -print0 | xargs -0 sed -i -f tg2vmw.sed # # Rename copyrights s/Tungsten Gra\(ph\|hp\)ics,\? [iI]nc\.\?\(, Cedar Park\)\?\(, Austin\)\?\(, \(Texas\|TX\)\)\?\.\?/VMware, Inc./g /Copyright/s/Tungsten Graphics\(,\? [iI]nc\.\)\?\(, Cedar Park\)\?\(, Austin\)\?\(, \(Texas\|TX\)\)\?\.\?/VMware, Inc./ s/TUNGSTEN GRAPHICS/VMWARE/g # Rename emails s/[email protected]/[email protected]/ s/[email protected]/[email protected]/g s/jrfonseca-at-tungstengraphics-dot-com/jfonseca-at-vmware-dot-com/ s/jrfonseca\[email protected]/[email protected]/g s/keithw\[email protected]/[email protected]/g s/[email protected]/[email protected]/g s/thomas-at-tungstengraphics-dot-com/thellstom-at-vmware-dot-com/ s/[email protected]/[email protected]/ # Remove dead links s@Tungsten Graphics (http://www.tungstengraphics.com)@Tungsten Graphics@g # C string src/gallium/state_trackers/vega/api_misc.c s/"Tungsten Graphics, Inc"/"VMware, Inc"/ Reviewed-by: Brian Paul <[email protected]>
* i965: Use SET_FIELD to safety check our x/y offsets in blits.Eric Anholt2014-01-091-7/+8
| | | | | | | | | | | | | | The earlier assert made sure that our math didn't exceed our bounds, but this makes sure that we don't overflow from the high bits X into the low bits of Y. We've already put checks in intel_miptree_blit(), but I've wanted to expand the type in our protoype from short to uint32_t, and we could get in trouble with intel_emit_linear_blit() if we did. v2: Add Ken's comment about the funny language extension used. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]> (v1) Reviewed-by: Anuj Phogat <[email protected]> (v1)
* i965: Add a safety check for emitting blits.Eric Anholt2014-01-091-0/+4
| | | | | | | | | | | | With all of the flipping and pitch twiddling and miptree layout involved in our blits, there are lots of ways for us to scribble outside of a buffer. Put in a check that we're not about to do so. This catches a bug that glamor was running into. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965: Don't call the blitter on addresses it can't handle.Eric Anholt2014-01-091-0/+20
| | | | | | | | | Noticed by tex3d-maxsize on my next commit to check that our addresses don't overflow. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965: Replace OUT_RELOC_FENCED with OUT_RELOC.Kenneth Graunke2013-12-091-12/+10
| | | | | | | | | | | | | | On Gen4+, OUT_RELOC_FENCED is equivalent to OUT_RELOC; libdrm silently ignores the fenced flag: /* We never use HW fences for rendering on 965+ */ if (bufmgr_gem->gen >= 4) need_fence = false; Thanks to Eric for noticing this. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Drop trailing whitespace from the rest of the driver.Kenneth Graunke2013-12-051-5/+5
| | | | | | | Performed via: $ for file in *; do sed -i 's/ *//g'; done Signed-off-by: Kenneth Graunke <[email protected]>
* i965: Convert brw->batch.is_blit to a BLT_RING/RENDER_RING enum.Kenneth Graunke2013-11-211-3/+3
| | | | | | | | Passing BLT_RING or RENDER_RING to batchbuffer functions is a lot more obvious than passing true or false. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Fix logic_op check.Vinson Lee2013-11-031-2/+1
| | | | | | | Fixes "Macro compares unsigned to 0" defect reported by Coverity. Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965: Delete the BATCH_LOCALS macro.Kenneth Graunke2013-08-011-2/+0
| | | | | | | | | This hasn't done anything in a long time, and it's only used in a couple places...which means we couldn't use it without doing a bunch of work anyway. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Delete intel_context entirely.Kenneth Graunke2013-07-091-2/+1
| | | | | | | | | | This makes brw_context inherit directly from gl_context; that was the only thing left in intel_context. Signed-off-by: Kenneth Graunke <[email protected]> Acked-by: Chris Forbes <[email protected]> Acked-by: Paul Berry <[email protected]> Acked-by: Anuj Phogat <[email protected]>
* i965: Move intel_context::gen and gt fields to brw_context.Kenneth Graunke2013-07-091-4/+2
| | | | | | | | | | Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <[email protected]> Acked-by: Chris Forbes <[email protected]> Acked-by: Paul Berry <[email protected]> Acked-by: Anuj Phogat <[email protected]>
* i965: Move intel_context::perf_debug to brw_context.Kenneth Graunke2013-07-091-1/+0
| | | | | | | Signed-off-by: Kenneth Graunke <[email protected]> Acked-by: Chris Forbes <[email protected]> Acked-by: Paul Berry <[email protected]> Acked-by: Anuj Phogat <[email protected]>
* i965: Move intel_context::batch to brw_context.Kenneth Graunke2013-07-091-3/+2
| | | | | | | Signed-off-by: Kenneth Graunke <[email protected]> Acked-by: Chris Forbes <[email protected]> Acked-by: Paul Berry <[email protected]> Acked-by: Anuj Phogat <[email protected]>
* i965: Pass brw_context to functions rather than intel_context.Kenneth Graunke2013-07-091-28/+30
| | | | | | | | | | | | | | This makes brw_context available in every function that used intel_context. This makes it possible to start migrating fields from intel_context to brw_context. Surprisingly, this actually removes some code, as functions that use OUT_BATCH don't need to declare "intel"; they just use "brw." Signed-off-by: Kenneth Graunke <[email protected]> Acked-by: Chris Forbes <[email protected]> Acked-by: Paul Berry <[email protected]> Acked-by: Anuj Phogat <[email protected]>
* i965: Replace #include "intel_context.h" with brw_context.h.Kenneth Graunke2013-07-091-1/+1
| | | | | | | | | | | brw_context.h includes intel_context.h, but additionally makes the brw_context structure available. Switching this allows us to start using brw_context in more places. Signed-off-by: Kenneth Graunke <[email protected]> Acked-by: Chris Forbes <[email protected]> Acked-by: Paul Berry <[email protected]> Acked-by: Anuj Phogat <[email protected]>
* i965: Drop i915-specific blit clear code.Eric Anholt2013-06-281-178/+0
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Drop #ifdef I915 code.Eric Anholt2013-06-281-8/+0
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Move the remaining intel code to the i965 directory.Eric Anholt2013-06-261-1/+770
| | | | | | | | | Now that i915's forked off, they don't need to live in a shared directory. Acked-by: Kenneth Graunke <[email protected]> Acked-by: Chad Versace <[email protected]> Acked-by: Adam Jackson <[email protected]> (and I hear second hand that idr is OK with it, too)
* [965] Enable EXT_framebuffer_object.Eric Anholt2007-12-201-617/+1
| | | | | To do so, merge the remainnig necessary code from the buffers, blit, span, and screen code to shared, and replace it with those.
* [965] Replace our own depth constants in intel context with GL context ones.Eric Anholt2007-12-171-1/+1
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* [intel] Cleanup of */intel_blit.c to bring the two closer.Eric Anholt2007-12-171-173/+176
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