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path: root/src/mesa/drivers/dri/i965/gen8_depth_state.c
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* i965/gen7-8: Set up early depth/stencil control appropriately for image load/...Francisco Jerez2015-08-111-3/+3
* i965: Move pipecontrol workaround bo to brw_pipe_controlChris Wilson2015-07-081-1/+1
* i965: Drop brw->depthstencil.stencil_offset from gen8_depth_state.c.Kenneth Graunke2015-06-251-5/+2
* i965: Rename intel_emit* to reflect their new location in brw_pipe_controlChris Wilson2015-06-241-1/+1
* i965: Fix whitespace error in gen8_depth_state.cKenneth Graunke2015-06-231-1/+1
* i965: Emit 3DSTATE_MULTISAMPLE before WM_HZ_OP (gen8+)Ben Widawsky2015-05-271-0/+10
* i965/state: Don't use brw->state.dirty.mesaJordan Justen2015-03-311-1/+1
* i965/skl: Don't use the PMA depth stall workaroundBen Widawsky2015-03-271-1/+6
* i965/gen8: Don't rely directly on the hiz miptree structureJordan Justen2015-03-091-3/+3
* i965/hiz: Start to separate miptree out from hiz buffersJordan Justen2015-03-091-3/+3
* i965: Rename some PIPE_CONTROL flagsBen Widawsky2015-03-021-1/+1
* i965/skl: Implement WaDisable1DDepthStencilNeil Roberts2015-02-101-0/+12
* i965: Move PSCDEPTH calculations from draw time to compile time.Kenneth Graunke2014-12-041-8/+4
* i965: Move BRW_NEW_*_PROG_DATA flags to .brw (not .cache).Kenneth Graunke2014-12-021-2/+2
* i965: Rename CACHE_NEW_*_PROG to BRW_NEW_*_PROG_DATA.Kenneth Graunke2014-12-021-3/+3
* i965: Use brw_wm_prog_data::uses_kill, not gl_fragment_program::UsesKillKenneth Graunke2014-11-271-2/+2
* i965: Implement the PMA stall fix.Kenneth Graunke2014-11-041-0/+170
* i965/skl: Use new MOCS for SKLKristian Høgsberg2014-11-031-4/+6
* Revert 5 i965 patches: 8e27a4d2, 373143ed, c5bdf9be, 6f56e142, 88e3d404Jordan Justen2014-09-041-1/+1
* i965: Create a macro for setting a dirty bit.Paul Berry2014-09-011-1/+1
* i965: Use unreachable() instead of unconditional assert().Matt Turner2014-07-011-1/+1
* i965: Use 8x4 aligned rectangles for HiZ operations on Broadwell.Kenneth Graunke2014-06-161-4/+16
* i965/gen8: Set depth extent fieldJordan Justen2014-05-131-1/+1
* i965/gen8 depth: Set depth size based on LOD0 for 3D texturesJordan Justen2014-05-131-2/+2
* i965/Gen8: Set up layer constraints properly for depth buffersChris Forbes2014-05-091-9/+6
* i965: Delete the intel_regions.c code.Eric Anholt2014-05-011-1/+0
* i965: Drop use of intel_region from miptrees.Eric Anholt2014-05-011-7/+7
* i965: Make Broadwell HiZ path arrange for TC flushes.Kenneth Graunke2014-04-221-0/+3
* i965/gen7: Skip repeated NULL depth/stencil state emits.Eric Anholt2014-04-111-0/+8
* i965: Set Broadwell MOCS values everywhere it's possible.Kenneth Graunke2014-03-251-3/+4
* i965: Implement HiZ resolves on Broadwell.Kenneth Graunke2014-02-191-0/+103
* i965: Refactor Gen8 depth packet emission.Kenneth Graunke2014-02-191-72/+99
* i965: Program 3DSTATE_HIER_DEPTH_BUFFER properly on Broadwell.Kenneth Graunke2014-02-191-8/+17
* i965: Update 3DSTATE_{DEPTH,STENCIL,...}_BUFFER and such for Broadwell.Kenneth Graunke2014-01-311-0/+169
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