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path: root/src/mesa/drivers/dri/i965/gen6_depth_state.c
Commit message (Expand)AuthorAgeFilesLines
* i965/gen6: Set up layer constraints properly for depth buffers.Kenneth Graunke2015-07-101-1/+5
* i965: Rename intel_emit* to reflect their new location in brw_pipe_controlChris Wilson2015-06-241-1/+1
* i965/hiz: Start to separate miptree out from hiz buffersJordan Justen2015-03-091-1/+1
* i965: Do Sandybridge workaround flushes before each primitive.Kenneth Graunke2015-02-171-7/+0
* i965/gen6: Stencil/hiz needs an offset for LOD > 0Jordan Justen2014-08-151-2/+32
* i965/gen6 depth surface: program 3DSTATE_DEPTH_BUFFER to top of surfaceJordan Justen2014-08-151-8/+27
* i965/gen6 depth surface: calculate minimum array element being renderedJordan Justen2014-08-151-0/+2
* i965/gen6 depth surface: calculate LOD being rendered toJordan Justen2014-08-151-0/+3
* i965/gen6 depth surface: calculate depth (array size) for depth surfaceJordan Justen2014-08-151-0/+3
* i965/gen6 depth surface: calculate more specific surface typeJordan Justen2014-08-151-0/+33
* i965/gen6_depth_state.c: Remove (gen != 6) code pathsJordan Justen2014-08-151-31/+14
* i965: Split gen6 depth hiz state out from brwJordan Justen2014-08-151-0/+176
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