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* i965: Fix fp fragment.position handling and enable HW part of ARB_fcc.Eric Anholt2010-01-261-1/+0
| | | | | | | | | As with swrast, this fixes the default pixel center behavior which was broken, and implements the previous behavior for integer. Fixes piglit fp-arb-fragment-coord-conventions-none. The extension won't be exposed until we get the GLSL part implemented. The DRI1 origin_x/y parts are dropped since they're no longer relevant.
* i965: Pack the brw_wm_prog_key better.Eric Anholt2009-11-191-1/+1
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* Merge branch 'outputswritten64'Ian Romanick2009-11-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Add a GLbitfield64 type and several macros to operate on 64-bit fields. The OutputsWritten field of gl_program is changed to use that type. This results in a fair amount of fallout in drivers that use programs. No changes are strictly necessary at this point as all bits used are below the 32-bit boundary. Fairly soon several bits will be added for clip distances written by a vertex shader. This will cause several bits used for varyings to be pushed above the 32-bit boundary. This will affect any drivers that support GLSL. At this point, only the i965 driver has been modified to support this eventuality. I did this as a "squash" merge. There were several places through the outputswritten64 branch where things were broken. I foresee this causing difficulties later for bisecting. The history is still available in the branch. Conflicts: src/mesa/drivers/dri/i965/brw_wm.h
* i965: Share OPCODE_TXB between brw_wm_emit.c and brw_wm_glsl.cEric Anholt2009-11-131-0/+7
| | | | This should fix TXB on G45 and older in the GLSL case.
* i965: Share OPCODE_TEX between brw_wm_emit.c and brw_wm_glsl.c.Eric Anholt2009-11-131-0/+8
| | | | | New comments should explain some of the confusion about how this message works.
* i965: avoid memsetting all the BRW_WM_MAX_INSN arrays for every compile.Eric Anholt2009-11-101-4/+4
| | | | | | | | | For an app that's blowing out the state cache, like sauerbraten, the memset of the giant arrays ended up taking 11% of the CPU even when only a "few" of the entries got used. With this, the WM program compile drops back down to 1% of CPU time. Bug #24981 (bisected to BRW_WM_MAX_INSN increase).
* i965: Share min/max between brw_wm_emit.c and brw_wm_glsl.cEric Anholt2009-11-061-0/+10
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* i965: Share emit_fb_write() between brw_wm_emit.c and brw_wm_glsl.cEric Anholt2009-11-061-0/+6
| | | | This should fix issues with antialiased lines in GLSL.
* i965: Share most of the WM functions between brw_wm_glsl.c and brw_wm_emit.cEric Anholt2009-11-061-0/+34
| | | | | The PINTERP code should be faster for brw_wm_glsl.c now since brw_wm_emit.c's had been improved, and pixel_w should no longer stomp on a neighbor to dst.
* i965: Share math functions between brw_wm_glsl.c and brw_wm_emit.c.Eric Anholt2009-11-061-0/+16
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* i965: Share the sop opcodes between brw_wm_glsl.c and brw_wm_emit.c.Eric Anholt2009-11-061-0/+6
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* i965: Share OPCODE_MAD between brw_wm_glsl.c and brw_wm_emit.cEric Anholt2009-11-061-0/+6
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* i965: Share the DP3, DP4, and DPH between brw_wm_glsl.c and brw_wm_emit.cEric Anholt2009-11-061-0/+15
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* i965: Add generic GLSL code for unaliasing a 3-arg opcode, and share LRP code.Eric Anholt2009-11-061-0/+6
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* i965: Share basic ALU ops between brw_wm_glsl and brw_wm_emit.cEric Anholt2009-11-061-0/+17
| | | | | This drops support for get_src_reg_imm in these, but the prospect of getting brw_wm_pass*.c onto our GLSL path is well worth some temporary pain.
* i965: Collect GLSL src/dst regs up in generic code.Eric Anholt2009-11-061-0/+2
| | | | | | | | This matches brw_wm_emit.c, which we'll be using shortly. There's a possible penalty here in that we'll allocate registers for unused channels, since we aren't doing ref tracking like brw_wm_pass*.c does. However, my measurements on GM965 don't show any for either OA or UT2004 with the GLSL path forced.
* i965: Fix BRW_WM_MAX_INSN to reflect current limits.Eric Anholt2009-10-301-2/+1
| | | | Part of fixing bug #24355.
* i965: make brw_wm_prog_key a little smallerBrian Paul2009-10-291-3/+3
| | | | | | | GLushort is big enough for the swizzle and origin fields. The key could probably be made smaller still by re-ordering things. I'll hold off on that until after the outputswritten64 branch is merged. The key will get a little larger again with the GLbitfield64 fields.
* i965: don't use context state in emit_fb_write()Brian Paul2009-10-291-0/+1
| | | | | Put the state that we care about in the hash key. Issue spotted by Keith Whitwell.
* i965: use macros to get/set prog_instruction::Aux fieldBrian Paul2009-10-291-0/+6
| | | | This makes things a bit easier to remember/understand.
* i965: Move OPCODE_DDX/DDY to brw_wm_emit.c and make it actually work.Eric Anholt2009-09-111-1/+7
| | | | | | | Previously, it was trying to mess around with the varying's WM setup data to produce a result. Along with not actually working when passed a varying, this wouldn't work if you did dFd[xy]() on a temporary. Instead, just calculate the derivative using the neighbors in the subspan.
* i965: drop dead scalar handling in GLSL.Eric Anholt2009-08-121-1/+0
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* i965: Store the dispatch width in the WM compile struct.Eric Anholt2009-08-121-0/+1
| | | | I'll be using this in merging brw_wm_emit.c and brw_wm_glsl.c
* i965: Handle scalar result swizzling in shared GLSL/non-GLSL code.Eric Anholt2009-08-121-0/+1
| | | | | This is preparation for merging of brw_wm_glsl.c and brw_wm_emit.c, and glsl.c doesn't swizzle channel results around.
* i965: Fix source depth reg setting for FSes reading and writing to depth.Eric Anholt2009-08-051-0/+1
| | | | | | | | For some IZ setups, we'd forget to account for the source depth register being present, so we'd both read the wrong reg, and write output depth to the wrong reg. Bug #22603.
* Merge branch 'mesa_7_5_branch'Brian Paul2009-06-161-1/+1
|\ | | | | | | | | | | Conflicts: src/mesa/main/api_validate.c
| * i965: fix bugs in projective texture coordinatesBrian Paul2009-06-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For the TXP instruction we check if the texcoord is really a 4-component atttibute which requires the divide by W step. This check involved the projtex_mask field. However, the projtex_mask field was being miscalculated because of some confusion between vertex program outputs and fragment program inputs. 1. Rework the size_masks calculation so we correctly set bits corresponding to fragment program input attributes. 2. Rename projtex_mask to proj_attrib_mask since we're interested in more than just texcoords (generic varying vars too). 3. Simply the indexing of the size_masks and proj_attrib_mask fields. 4. The tracker::active[] array was mis-dimensioned. Use MAX_PROGRAM_TEMPS instead of a magic number. 5. Update comments, add new assertions. With these changes the Lightsmark demo/benchmark renders correctly, until we eventually hit a GPU lockup...
| * i965: only upload constant buffer data when we actually need the const bufferBrian Paul2009-04-271-2/+0
| | | | | | | | | | | | | | Make the use_const_buffer field per-program and only call the code which updates the constant buffer's data if the flag is set. This should undo the perf regression from 20f3497e4b6756e330f7b3f54e8acaa1d6c92052
* | i965: interpolate colors with perspective correction by defaultBrian Paul2009-06-121-0/+1
| | | | | | | | | | | | | | ...rather than with linear interpolation. Modern hardware should use perspective-corrected interpolation for colors (as for texcoords). glHint(GL_PERSPECTIVE_CORRECTION_HINT, mode) can be used to get linear interpolation if mode = GL_FASTEST.
* | i965: Fix register allocation of GLSL fp inputs.Eric Anholt2009-05-141-0/+1
| | | | | | | | | | | | | | | | | | Before, if the VP output something that is in the attributes coming into the WM but which isn't used by the WM, then WM would end up reading subsequent varyings from the wrong places. This was visible with a GLSL demo using gl_PointSize in the VS and a varying in the WM, as point size is in the VUE but not used by the WM. There is now a regression test in piglit, glsl-unused-varying.
* | i965: don't use GRF regs 126,127 for WM programsBrian Paul2009-05-081-0/+2
| | | | | | | | | | | | | | They seem to be used for something else and using them for shader temps seems to lead to GPU lock-ups. Call _mesa_warning() when we run out of temps. Also, clean up some debug code.
* | i965: only upload constant buffer data when we actually need the const bufferBrian Paul2009-04-271-2/+0
| | | | | | | | | | | | | | | | | | Make the use_const_buffer field per-program and only call the code which updates the constant buffer's data if the flag is set. This should undo the perf regression from 20f3497e4b6756e330f7b3f54e8acaa1d6c92052 (cherry picked from master, commit dc9705d12d162ba6d087eb762e315de9f97bc456)
* | i965: rework GLSL/WM register allocationBrian Paul2009-04-241-1/+4
|/ | | | | | | | | Use a bitvector of used/free flags. If we run out of temps, examine the live intervals of the temp regs in the program and free those which are no longer alive. Also, enable the new WM const buffer code.
* i965: another checkpoint commit of new constant buffer supportBrian Paul2009-04-031-0/+8
| | | | | Everything is in place now for using a true constant buffer for GLSL fragment shaders. Still some bugs to find though.
* i965: fix indentationBrian Paul2009-04-031-2/+2
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* i965: Fix glFrontFacing in twoside GLSL demo.Eric Anholt2009-03-231-1/+2
| | | | | | | This also cuts instructions by just using the existing bit in the payload rather than computing it from the determinant in the SF unit and passing it as a varying down to the WM. Something still goes wrong with getting the backface color right, but a simpler shader appears to get the right result.
* i965: remove unused PROGRAM_INTERNAL_PARAM, added commentBrian Paul2009-03-131-3/+1
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* i965: commentsBrian Paul2009-03-061-0/+2
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* i965: use the new prog_instruction::TexShadow fieldBrian Paul2009-02-201-0/+1
| | | | | GLSL shadow() sampler calls are properly propogated down to the driver now. The glean glsl1 shadow() tests work (except for the alpha channel).
* i965: rewrite the code for handling shader subroutine callsBrian Paul2009-02-131-0/+2
| | | | | | | | | | | | | | | | | | Previously, the prog_instruction::Data field was used to map original Mesa instructions to brw instructions in order to resolve subroutine calls. This was a rather tangled mess. Plus it's an obstacle to implementing dynamic allocation/growing of the instruction buffer (it's still a fixed size). Mesa's GLSL compiler emits a label for each subroutine and CAL instruction. Now we use those labels to patch the subroutine calls after code generation has been done. We just keep a list of all CAL instructions that needs patching and a list of all subroutine labels. It's a simple matter to resolve them. This also consolidates some redundant post-emit code between brw_vs_emit.c and brw_wm_glsl.c and removes some loops that cleared the prog_instruction::Data fields at the end. Plus, a bunch of new comments.
* i965: implement GL_EXT_texture_swizzleBrian Paul2009-01-281-0/+2
| | | | | If the texture swizzle is not XYZW (no-op) add an extra MOV instruction after the TEX instruction to rearrange the components.
* i965: remove pad fieldBrian Paul2009-01-281-1/+0
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* i965: widen per-texture bitfields for 16 texture image unitsBrian Paul2009-01-281-5/+5
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* i915: Remove dead early z enable bit which was always on.Eric Anholt2008-11-281-2/+1
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* i965: implement the missing OPCODE_NOISE1 and OPCODE_NOISE2 instructions.Gary Wong2008-10-311-0/+2
| | | | (Only in fragment shaders, so far. Support for NOISE3 and NOISE4 to come.)
* i965: Allocate temporaries contiguously with other regs in fragment shaders.Gary Wong2008-10-281-0/+2
| | | | | This is required for threads to be spawned with correctly sized GRF register blocks.
* [i965] multiple rendering target fixZou Nan hai2008-03-211-0/+1
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* [i965] multiple rendering target supportZou Nan hai2008-03-131-0/+2
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* [i965] fix fd.o bug #11471 and #11478Zou Nan hai2008-03-071-1/+2
| | | | | 1. Follow EXT_texture_rectangle with YCbCr texture 2. swap UV component for MESA_FORMAT_YCBCR
* [965] Bug #9151: make fragment.position return window coords not screen coords.Eric Anholt2008-02-281-0/+2
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