aboutsummaryrefslogtreecommitdiffstats
path: root/src/mesa/drivers/dri/i965/brw_wm.c
Commit message (Collapse)AuthorAgeFilesLines
* i965: added OPCODE_NRM3/4Brian Paul2009-01-011-0/+3
|
* i965: Fix stray character that the compile whined about.Eric Anholt2008-12-031-0/+0
|
* i915: Remove dead early z enable bit which was always on.Eric Anholt2008-11-281-0/+0
|
* Revert "Revert "Merge branch 'drm-gem'""Dave Airlie2008-08-241-3/+1
| | | | This reverts commit 7c81124d7c4a4d1da9f48cbf7e82ab1a3a970a7a.
* Revert "Merge branch 'drm-gem'"Dave Airlie2008-08-241-1/+3
| | | | | | | | This reverts commit 53675e5c05c0598b7ea206d5c27dbcae786a2c03. Conflicts: src/mesa/drivers/dri/i965/brw_wm_surface_state.c
* i965: Enable GL_ARB_fragment_program_shadow and fix key->shadowtex_mask. ↵Xiang, Haihao2008-08-201-6/+3
| | | | (bug #16852, #16853)
* intel-gem: Update to new check_aperture API for classic mode.Eric Anholt2008-08-081-3/+1
| | | | | | To do this, I had to clean up some of 965 state upload stuff. We may end up over-emitting state in the aperture overflow case, but that should be rare, and I'd rather have the simplification of state management.
* i965: initial attempt at fixing the aperture overflowDave Airlie2008-04-181-2/+4
| | | | | | | | | Makes state emission into a 2 phase, prepare sets things up and accounts the size of all referenced buffer objects. The emit stage then actually does the batchbuffer touching for emitting the objects. There is an assert in dri_emit_reloc if a reloc occurs for a buffer that hasn't been accounted yet.
* [i965] multiple rendering target supportZou Nan hai2008-03-131-4/+1
|
* [i965] fix fd.o bug #11471 and #11478Zou Nan hai2008-03-071-2/+6
| | | | | 1. Follow EXT_texture_rectangle with YCbCr texture 2. swap UV component for MESA_FORMAT_YCBCR
* [965] Bug #9151: make fragment.position return window coords not screen coords.Eric Anholt2008-02-281-1/+25
|
* i965: remove unused hal hooksDave Airlie2008-02-141-19/+0
| | | | These don't appear to have ever been used.
* i965: new integrated graphics chipset supportXiang, Haihao2008-01-291-2/+2
|
* [965] Fix and enable separate stencil.Eric Anholt2007-12-211-1/+2
| | | | | | Note that this does not enable GL_EXT_stencil_two_side, because Mesa's computed _TestTwoSide ends up respecting only STENCIL_TEST_TWO_SIDE_EXT (defaults to GL_FALSE), even if the application uses only GL 2.0 / ATI entrypoints.
* [965] Replace the state cache suballocator with direct dri_bufmgr use.Eric Anholt2007-12-141-16/+14
| | | | | | | | | | | | | | | | | | | | | | | The user-space suballocator that was used avoided relocation computations by using the general and surface state base registers and allocating those types of buffers out of pools built on top of single buffer objects. It also avoided calls into the buffer manager for these small state allocations, since only one buffer object was being used. However, the buffer allocation cost appears to be low, and with relocation caching, computing relocations for buffers is essentially free. Additionally, implementing the suballocator required a don't-fence-subdata flag to disable waiting on buffer maps so that writing new data didn't block on rendering using old data, and careful handling when mapping to update old data (which we need to do for unavoidable relocations with FBOs). More importantly, when the suballocator filled, it had no replacement algorithm and just threw out all of the contents and forced them to be recomputed, which is a significant cost. This is the first step, which just changes the buffer type, but doesn't yet improve the hash table to not result in full recompute on overflow. Because the buffers are all allocated out of the general buffer allocator, we can no longer use the general/surface state bases to avoid relocations, and they are set to 0 instead.
* Revert "[965] Add missing flagging of new stage programs for updating stage ↵Eric Anholt2007-12-051-19/+7
| | | | | | | | | state." I had forgotten part of brw_state_cache.c that made this fix not relevant for master (last_addr comparison and flagging based on cache id). This reverts commit a4642f3d18bdaebaba31e5dee72fe5de9d890ffb.
* [965] Add missing flagging of new stage programs for updating stage state.Eric Anholt2007-12-051-7/+19
| | | | | | Otherwise, choosing a new program wouldn't necessarily update the state, and and an old program could be executed, leading to various sorts of pretty pictures or hangs.
* Merge branch '965-glsl'Zou Nan hai2007-10-261-39/+45
|\ | | | | | | | | | | | | Conflicts: src/mesa/drivers/dri/i965/brw_sf.h src/mesa/drivers/dri/i965/intel_context.c
| * support branch and loop in pixel shaderZou Nan hai2007-06-211-39/+41
| | | | | | | | most of the sample working with some small modification
| * Initial 965 GLSL supportZou Nan hai2007-04-121-0/+4
| |
* | i965: fix projtex_maskXiang, Haihao2007-08-131-1/+1
|/ | | | | projtex_mask is only an 8bit field, and wm.input_size_masks includes other attributes' information, therefore right shift is needed.
* Update DRI drivers for new glsl compiler.Brian2007-02-231-4/+0
| | | | | | Mostly: - update #includes - update STATE_* token code
* i965: Fix a crash with wine by not allocating >1MB on the stack.Eric Anholt2006-12-091-19/+30
|
* Add Intel i965G/Q DRI driver.Eric Anholt2006-08-091-0/+349
This driver comes from Tungsten Graphics, with a few further modifications by Intel.