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path: root/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
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* i965: Add src/dst interference for certain instructions with hazards.Kenneth Graunke2015-11-301-0/+13
* i965: Clean up #includes in the compiler.Matt Turner2015-11-241-2/+0
* i965: Rename GRF to VGRF.Matt Turner2015-11-131-13/+13
* i965: Use brw_reg's nr field to store register number.Matt Turner2015-11-131-18/+18
* i965/vec4: Don't unspill the same register in consecutive instructionsIago Toral Quiroga2015-09-041-8/+118
* util/ra: Make allocating conflict lists optionalJason Ekstrand2015-08-181-1/+1
* i965/reg_allocate: Use make_reg_conflicts_transitiveJason Ekstrand2015-08-181-1/+4
* i965/vec4: Fix indentation in vec4_visitor::evaluate_spill_costsIago Toral Quiroga2015-08-071-12/+12
* i965/vec4: Move c->last_scratch into vec4_visitor.Kenneth Graunke2015-07-091-1/+1
* i965: Remove the brw_context from the visitorsJason Ekstrand2015-06-231-1/+0
* i965: Add a brw_compiler structure and store the register sets in itJason Ekstrand2015-04-221-19/+19
* i965: Remove useless reg_offset >= 0 tests.Matt Turner2015-04-111-1/+0
* Fix invalid extern "C" around header inclusion.Mark Janes2015-03-051-3/+0
* i965/vec4: Calculate register allocation q values manually.Francisco Jerez2015-02-191-1/+17
* i965/vec4: Take into account non-zero reg_offset during register allocation.Francisco Jerez2015-02-101-1/+3
* i965/vec4: Add register classes up to MAX_VGRF_SIZE.Francisco Jerez2015-02-101-4/+6
* i965: Factor out virtual GRF allocation to a separate object.Francisco Jerez2015-02-101-22/+21
* i965/vec4: Drop writemasks on scratch reads.Kenneth Graunke2014-12-121-8/+0
* i965/vec4: Don't use instruction list after calculating the cfg.Matt Turner2014-09-241-4/+4
* i965: Remove now unneeded calls to calculate_cfg().Matt Turner2014-09-241-2/+0
* i965: Remove cfg-invalidating parameter from invalidate_live_intervals.Matt Turner2014-09-241-1/+1
* i965/vec4: Preserve CFG in spill_reg().Matt Turner2014-09-241-4/+7
* mesa: Move register_allocate.c to util.Eric Anholt2014-09-231-1/+1
* ra: cleanup the public APIConnor Abbott2014-08-131-1/+1
* i965: Make a common backend_reg class.Matt Turner2014-07-051-1/+1
* i965: Use typed foreach_in_list instead of foreach_list.Matt Turner2014-07-011-15/+5
* i965: Allocate register sets at screen creation, not context creation.Kenneth Graunke2014-03-181-18/+20
* i965/vec4: Fix off-by-one register class overallocation.Francisco Jerez2014-02-191-1/+1
* glsl: Convert piles of foreach_iter to the newer foreach_list macro.Kenneth Graunke2014-01-131-4/+4
* i965/vec4: Add invalidate_live_intervals method.Matt Turner2013-11-201-1/+1
* i965: Merge together opcodes for SHADER_OPCODE_GEN4_SCRATCH_READ/WRITEEric Anholt2013-10-301-2/+2
* i965/vec4: Add the ability to suppress register spilling.Paul Berry2013-10-241-1/+4
* i965: Move vec4 register allocation data structures to brw->vec4.Paul Berry2013-08-311-15/+16
* i965/vs: Allocate register set once at context creation.Kenneth Graunke2013-08-261-4/+2
* i965/vs: Move base_reg_count computation to brw_alloc_reg_set().Kenneth Graunke2013-08-261-3/+4
* i965/vs: Expose the payload registers to the register allocator.Kenneth Graunke2013-08-261-6/+34
* i965/vs: Use a fixed set of register classes.Kenneth Graunke2013-08-261-37/+13
* i965: Stop including brw_vs.h from brw_vec4.h.Paul Berry2013-08-231-0/+1
* i965: Move intel_context::gen and gt fields to brw_context.Kenneth Graunke2013-07-091-3/+1
* glsl: Remove ir_print_visitor.h includes and usageEric Anholt2013-06-211-1/+0
* i965/vs: Do round-robin register allocation on gen6+ like we do in the FS.Eric Anholt2013-05-021-0/+4
* i965/vs: move VS-specific data members to vs_vec4_visitor.Paul Berry2013-04-111-6/+6
* i965/vs: split brw_vs_prog_data into generic and VS-specific parts.Paul Berry2013-04-111-5/+5
* i965/vs: split brw_vs_compile into generic and VS-specific parts.Paul Berry2013-04-111-1/+1
* i965/vs: Do the temporary allocation in emit_scratch_write().Eric Anholt2012-10-171-10/+1
* i965/vs: Simplify emit_scratch_write() prototype.Eric Anholt2012-10-171-1/+1
* i965/vs: Try again when we've successfully spilled a reg.Eric Anholt2012-10-101-7/+10
* i965/vs: Implement register spilling.Kenneth Graunke2012-10-101-1/+127
* ra: Add q_values parameter to ra_set_finalize()Tom Stellard2012-09-191-1/+1
* intel: Fix signed/unsigned comparison warnings.Eric Anholt2012-05-141-3/+3
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