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path: root/src/mesa/drivers/dri/i965/brw_vec4.cpp
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* i965: Prevent implicit upcasts to brw_reg.Matt Turner2015-11-241-2/+3
* i965: Use scope operator to ensure brw_reg is interpreted as a type.Matt Turner2015-11-241-2/+2
* i965: Use implicit backend_reg copy-constructor.Matt Turner2015-11-241-4/+2
* i965: Add and use backend_reg::equals().Matt Turner2015-11-241-4/+2
* i965: Use nir_lower_tex for texture coordinate loweringJason Ekstrand2015-11-231-0/+2
* i965: Move postprocess_nir to codegen timeJason Ekstrand2015-11-231-1/+5
* i965: Drop IMM fs_reg/src_reg -> brw_reg conversions.Matt Turner2015-11-191-5/+1
* i965/vec4: Replace src_reg(imm) constructors with brw_imm_*().Matt Turner2015-11-191-55/+12
* i965: Convert scalar_* flags to a scalar_stage array.Kenneth Graunke2015-11-161-2/+2
* i965: Use BRW_MRF_COMPR4 macro in more places.Matt Turner2015-11-131-1/+1
* i965: Combine register file field.Matt Turner2015-11-131-10/+6
* i965: Replace HW_REG with ARF/FIXED_GRF.Matt Turner2015-11-131-83/+58
* i965: Rename GRF to VGRF.Matt Turner2015-11-131-16/+16
* i965: Use brw_reg's nr field to store register number.Matt Turner2015-11-131-52/+48
* i965: Unwrap some lines.Matt Turner2015-11-131-4/+1
* i965/vec4: Remove swizzle/writemask fields from src/dst_reg.Matt Turner2015-11-131-2/+0
* i965: Remove fixed_hw_reg field from backend_reg.Matt Turner2015-11-131-63/+47
* i965: Use immediate storage in inherited brw_reg.Matt Turner2015-11-131-19/+20
* i965: Make 'dw1' and 'bits' unnamed structures in brw_reg.Matt Turner2015-11-131-20/+20
* i965: Print force_writemask_all in dump_instructions().Kenneth Graunke2015-11-111-0/+3
* i965/vec4/skl+: Use ld2dms_w instead of ld2dmsNeil Roberts2015-11-051-0/+1
* i965: Replace default case with list of enum values.Matt Turner2015-11-021-8/+11
* i965/vec4: Wrap vec4_generator in a C function.Kenneth Graunke2015-10-291-3/+3
* i965/vec4: Convert src_reg/dst_reg to brw_reg at the end of the visitor.Kenneth Graunke2015-10-291-0/+86
* i965: remove unneeded src_reg copy in emit_shader_time_writeEmil Velikov2015-10-281-1/+1
* i965/vec4: print predicate control at brw_vec4 dump_instructionAlejandro Piñeiro2015-10-221-2/+3
* i965/vec4: adding vec4_cmod_propagation optimizationAlejandro Piñeiro2015-10-221-0/+1
* i965: Remove block arg from foreach_inst_in_block_*_starting_fromNeil Roberts2015-10-211-1/+1
* i965: Extract can_change_source_types() functions.Matt Turner2015-10-191-0/+12
* i965/vs: Move URB entry_size and read_length calculations to compile_vsJason Ekstrand2015-10-191-0/+34
* i965: Rename brw_foo_emit to brw_compile_fooJason Ekstrand2015-10-191-10/+10
* i965/vs: Rework vs_emit to take a nir_shader and a brw_compilerJason Ekstrand2015-10-191-43/+27
* i965/vec4: Remove gl_program and gl_shader_program from the generatorJason Ekstrand2015-10-191-2/+2
* i965/fs: Remove the gl_program from the generatorJason Ekstrand2015-10-191-1/+1
* i965/vs: Unify URB entry size/read length calculations between backends.Kenneth Graunke2015-10-101-18/+1
* i965: Move brw_get_shader_time_index() call out of emit functionsKristian Høgsberg Kristensen2015-10-081-6/+3
* i965: Move brw_dump_ir() out of brw_*_emit() functionsKristian Høgsberg Kristensen2015-10-081-7/+0
* i965: Generalize predicated break pass for use in vec4 backend.Matt Turner2015-10-051-0/+1
* i965/shader: Get rid of the shader, prog, and shader_prog fieldsJason Ekstrand2015-10-021-5/+4
* i965/fs,vec4: Get rid of the sanity_param_countJason Ekstrand2015-10-021-9/+0
* i965/vec4: Use nir info instead of pulling things out of [shader_]progJason Ekstrand2015-10-021-4/+4
* i965: Move binding table setup to codegen time.Jason Ekstrand2015-10-021-9/+0
* i965/shader: Pull assign_common_binding_table_offsets out of backend_shaderJason Ekstrand2015-10-021-1/+2
* i965/vec4: Get rid of the uniform_vector_size arrayJason Ekstrand2015-10-021-1/+0
* i965/vec4: Use the actual channels used in pack_uniform_registersJason Ekstrand2015-10-021-14/+37
* i965/vs: Move lazy NIR creation to codegen_vs_progJason Ekstrand2015-10-021-12/+0
* i965/vec4: Always use NIRJason Ekstrand2015-10-021-31/+8
* i965/vec4: Implement VS_OPCODE_GET_BUFFER_SIZESamuel Iglesias Gonsalvez2015-09-251-0/+1
* i965/vec4: Don't coalesce regs in Gen6 MATH ops if reswizzle/writemask neededAntia Puentes2015-09-231-2/+10
* i965/vec4: Detect and delete useless MOVs.Matt Turner2015-09-221-0/+22
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