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path: root/src/mesa/drivers/dri/i965/brw_vec4.cpp
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* i965/vec4: Fix mapping attributesJuan A. Suarez Romero2017-01-131-1/+1
* i965/vec4: take into account doubles when creating attribute mappingAlejandro Piñeiro2017-01-121-4/+9
* i965/vec4: use attribute slots for first non payload GRFAlejandro Piñeiro2017-01-121-1/+1
* nir/i965: use two slots from inputs_read for dvec3/dvec4 vertex input attributesJuan A. Suarez Romero2017-01-091-6/+5
* i965: Print VS output VUE map in Vulkan too.Kenneth Graunke2017-01-051-0/+5
* i965/vec4: run scalarize_df() after spillingIago Toral Quiroga2017-01-031-0/+18
* i965/vec4: prevent src/dst hazards during 64-bit register allocationIago Toral Quiroga2017-01-031-1/+7
* i965/vec4/scalarize_df: support more swizzles via vstride=0Iago Toral Quiroga2017-01-031-20/+48
* i965/vec4/scalarize_df: do not scalarize swizzles that we can support nativelyIago Toral Quiroga2017-01-031-25/+108
* i965/vec4: split instructions that read 64-bit interleaved attributesIago Toral Quiroga2017-01-031-2/+26
* i965/vec4: dump subnr for FIXED_GRFIago Toral Quiroga2017-01-031-1/+1
* i965/vec4: fix attribute setup for doublesIago Toral Quiroga2017-01-031-7/+14
* i965/vec4: fix indentation in lower_attributes_to_hw_regs()Iago Toral Quiroga2017-01-031-8/+8
* i965/vec4: make emit_pull_constant_load support 64-bit loadsIago Toral Quiroga2017-01-031-19/+6
* i965/vec4: fix move_push_constants_to_pull_constants() for 64-bit dataIago Toral Quiroga2017-01-031-4/+19
* i965/vec4: fix indentation in move_push_constants_to_pull_constants()Iago Toral Quiroga2017-01-031-30/+30
* i965/vec4: do not split scratch read/write opcodesIago Toral Quiroga2017-01-031-0/+9
* i965/vec4: Do not use DepCtrl with 64-bit instructionsIago Toral Quiroga2017-01-031-1/+13
* i965/vec4: extend the DWORD multiply DepCtrl restriction to all gen8 platformsIago Toral Quiroga2017-01-031-3/+6
* i965/vec4: Lower 64-bit MADIago Toral Quiroga2017-01-031-0/+44
* i965/vec4: Skip swizzle to subnr in 3src instructions with DF operandsIago Toral Quiroga2017-01-031-1/+4
* i965/vec4: fix indentation in pack_uniform_registersIago Toral Quiroga2017-01-031-15/+15
* i965/vec4: fix pack_uniform_registers for doublesIago Toral Quiroga2017-01-031-2/+9
* i965/vec4: teach register coalescing about 64-bitIago Toral Quiroga2017-01-031-3/+19
* i965/vec4: implement access to DF source components Z/WIago Toral Quiroga2017-01-031-0/+21
* i965/vec4: translate 64-bit swizzles to 32-bitIago Toral Quiroga2017-01-031-3/+46
* i965/vec4: add a scalarization pass for double-precision instructionsIago Toral Quiroga2017-01-031-0/+91
* i965/vec4: split double-precision SELIago Toral Quiroga2017-01-031-0/+6
* i965/vec4: dump NibCtrl for instructions with execsize != 8Iago Toral Quiroga2017-01-031-0/+3
* i965/vec4: add a SIMD lowering passIago Toral Quiroga2017-01-031-0/+159
* i965/vec4: handle 32 and 64 bit channels in liveness analysisJuan A. Suarez Romero2017-01-031-1/+1
* i965/vec4: dump the instruction execution sizeIago Toral Quiroga2017-01-031-1/+2
* i965/vec4: fix regs_read() for doublesIago Toral Quiroga2017-01-031-2/+2
* i965/vec4: Rename DF to/from F generator opcodesIago Toral Quiroga2017-01-031-4/+4
* i965/vec4: make opt_vector_float ignore doublesIago Toral Quiroga2017-01-031-0/+1
* i965/vec4: add VEC4_OPCODE_SET_{LOW,HIGH}_32BIT opcodesIago Toral Quiroga2017-01-031-0/+4
* i965/vec4: add VEC4_OPCODE_PICK_{LOW,HIGH}_32BIT opcodesIago Toral Quiroga2017-01-031-0/+4
* i965/vec4: set correct register regions for 32-bit and 64-bitIago Toral Quiroga2017-01-031-4/+9
* i965/vec4: add double/float conversion pseudo-opcodesIago Toral Quiroga2017-01-031-0/+8
* i965/vec4: add support for printing DF immediatesConnor Abbott2017-01-031-0/+3
* nir: pass compiler rather than devinfo to functions that call nir_optimizeTimothy Arceri2016-12-231-3/+2
* i965: Store a clip_distance_mask field similar to cull_distance_mask.Kenneth Graunke2016-11-191-0/+2
* i965: Use shader_info for brw_vue_prog_data::cull_distance_mask.Kenneth Graunke2016-11-191-0/+4
* nir/i965/anv/radv/gallium: make shader info a pointerTimothy Arceri2016-10-261-7/+9
* i965: Silence unused parameter warningsIan Romanick2016-10-171-1/+1
* i965/ir: Skip eliminate_find_live_channel() for stages with sparse thread dis...Francisco Jerez2016-09-211-0/+8
* i965/vec4: Assert that ATTR regions are register-aligned.Francisco Jerez2016-09-141-0/+1
* i965/vec4: Assign correct destination offset to rewritten instruction in regi...Francisco Jerez2016-09-141-2/+1
* i965/vec4: Don't coalesce registers with overlapping writes not matching the ...Francisco Jerez2016-09-141-4/+6
* i965/vec4: Compare full register offsets in opt_register_coalesce nop move ch...Francisco Jerez2016-09-141-1/+1
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