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path: root/src/mesa/drivers/dri/i965/brw_vec4.cpp
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* i965/ir: Skip eliminate_find_live_channel() for stages with sparse thread dis...Francisco Jerez2016-09-211-0/+8
* i965/vec4: Assert that ATTR regions are register-aligned.Francisco Jerez2016-09-141-0/+1
* i965/vec4: Assign correct destination offset to rewritten instruction in regi...Francisco Jerez2016-09-141-2/+1
* i965/vec4: Don't coalesce registers with overlapping writes not matching the ...Francisco Jerez2016-09-141-4/+6
* i965/vec4: Compare full register offsets in opt_register_coalesce nop move ch...Francisco Jerez2016-09-141-1/+1
* i965/vec4: Check that the write offsets match when setting dependency controls.Francisco Jerez2016-09-141-0/+2
* i965/vec4: Change opt_vector_float to keep track of the last offset seen in b...Francisco Jerez2016-09-141-3/+3
* i965/vec4: Simplify src/dst_reg to brw_reg conversion by using byte_offset().Francisco Jerez2016-09-141-7/+8
* i965/ir: Update several stale comments.Francisco Jerez2016-09-141-4/+4
* i965/ir: Don't print ARF subnr values twice.Francisco Jerez2016-09-141-4/+0
* i965/vec4: Print src/dst_reg::offset field consistently for all register files.Francisco Jerez2016-09-141-6/+15
* i965/vec4: Drop backend_reg::in_range() in favor of regions_overlap().Francisco Jerez2016-09-141-6/+8
* i965/vec4: Replace vec4_instruction::regs_read with ::size_read using byte un...Francisco Jerez2016-09-141-10/+20
* i965/vec4: Replace vec4_instruction::regs_written with ::size_written field i...Francisco Jerez2016-09-141-3/+3
* i965/vec4: Add wrapper functions for vec4_instruction::regs_read and ::regs_w...Francisco Jerez2016-09-141-2/+2
* i965/vec4: Replace dst/src_reg::reg_offset with dst/src_reg::offset expressed...Francisco Jerez2016-09-141-29/+32
* intel: s/brw_device_info/gen_device_info/Jason Ekstrand2016-09-031-3/+3
* i965/vec4: Ignore swizzle of VGRF for use by var_range_end().Matt Turner2016-08-191-1/+1
* i965/vec4: Make opt_vector_float reset at the top of each blockJason Ekstrand2016-08-101-80/+82
* i965/fs: calculate first non-payload GRF using attrib slotsJuan A. Suarez Romero2016-05-171-0/+1
* i965/vec4: use attribute slots to calculate URB read lengthJuan A. Suarez Romero2016-05-171-3/+9
* i965/fs: Stop setting dispatch_grf_start_reg from the visitorJason Ekstrand2016-05-141-0/+2
* i965: Pass devinfo pointer to is_3src() helpers.Francisco Jerez2016-05-031-1/+1
* i965: Pass devinfo pointer to brw_instruction_name().Francisco Jerez2016-05-031-1/+1
* i965: Properly handle integer types in opt_vector_float().Kenneth Graunke2016-04-201-4/+18
* i965: Make opt_vector_float() only handle non-type-conversion MOVs.Kenneth Graunke2016-04-201-2/+5
* i965: Fold vectorize_mov() back into the one caller.Kenneth Graunke2016-04-201-24/+16
* i965: Rework opt_vector_float() control flow.Kenneth Graunke2016-04-201-27/+34
* i965/vec4: Handle MOV_INDIRECT in pack_uniform_registersJason Ekstrand2016-04-151-0/+18
* i965/vec4: Add support for SHADER_OPCODE_MOV_INDIRECTJason Ekstrand2016-04-151-0/+1
* i965/vec4: Use can_do_writemask in can_reswizzleJason Ekstrand2016-04-151-3/+5
* i965/vec4: Move can_do_writemask to vec4_instructionJason Ekstrand2016-04-151-0/+28
* i965/vec4: Get rid of the uniform_size arrayJason Ekstrand2016-04-141-8/+0
* i965/vec4: Use MOV_INDIRECT instead of reladdr for indirect push constantsJason Ekstrand2016-04-141-1/+1
* i965: Remove the RCP+RSQ algebraic optimizationsJason Ekstrand2016-03-221-11/+0
* i965/vec4: Consider removal of no-op MOVs as progress during register coalesce.Francisco Jerez2016-03-141-0/+1
* i965/vec4: add opportunistic behaviour to opt_vector_float()Juan A. Suarez Romero2016-03-041-21/+39
* i965: Eliminate brw_nir_lower_{inputs,outputs,io} functions.Kenneth Graunke2016-02-261-3/+3
* i965: Lower min/max after optimization on Gen4/5.Matt Turner2016-02-171-0/+38
* i965: Fix gl_DrawID in the vec4 backend.Kenneth Graunke2016-02-141-5/+5
* i965: Rename optimizer debug 00 filenameBen Widawsky2016-02-121-1/+1
* i965/vec4: Drop support for ATTR as an instruction destination.Kenneth Graunke2016-02-091-16/+0
* i965: Apply VS attribute workarounds in NIR.Kenneth Graunke2016-02-091-0/+3
* i965: Explicitly write the "TR DS Cache Disable" bit at TCS EOT.Kenneth Graunke2016-02-091-1/+1
* i965/fs/generator: Take an actual shader stage rather than a stringJason Ekstrand2016-01-151-1/+1
* i965: Make an is_scalar boolean in brw_compile_vs().Kenneth Graunke2016-01-141-5/+5
* i965: Move 3-src subnr swizzle handling into the vec4 backend.Kenneth Graunke2016-01-021-0/+13
* i965: Add support for gl_DrawIDARB and enable extensionKristian Høgsberg Kristensen2015-12-291-1/+12
* i965: Add support for gl_BaseVertexARB and gl_BaseInstanceARBKristian Høgsberg Kristensen2015-12-291-2/+5
* i965: Don't set interleave or complete on TCS EOT message.Kenneth Graunke2015-12-281-0/+1
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