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path: root/src/mesa/drivers/dri/i965/brw_tex_layout.c
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* i965/miptree: Rename align_w,align_h -> halign,valignChad Versace2015-09-301-31/+31
* i965: refactor miptree alignment calculation codeNanley Chery2015-08-261-55/+30
* i965: change the meaning of cpp for compressed texturesNanley Chery2015-08-261-6/+9
* i965: correct mt->align_h for 2D textures on SkylakeNanley Chery2015-08-261-3/+8
* i965: use ALIGN_NPOT for setting ASTC mipmap layoutsNanley Chery2015-08-261-13/+13
* i965: Resolve GCC sign-compare warning.Rhys Kidd2015-08-181-1/+1
* i965: Add SKL support to brw_miptree_get_horizontal_slice_pitch().Francisco Jerez2015-08-111-3/+1
* i965: Rename MIPTREE_LAYOUT_ALLOC_* -> MIPTREE_LAYOUT_TILING_*.Matt Turner2015-08-061-4/+4
* Delete duplicate function is_power_of_two() and use _mesa_is_pow_two()Anuj Phogat2015-07-291-4/+4
* Revert "i965/gen9: Plugin the code for selecting YF/YS tiling on skl+"Anuj Phogat2015-07-211-92/+17
* i965: Push miptree tiling request into flagsBen Widawsky2015-07-161-10/+11
* Revert "i965: Push miptree tiling request into flags"Ben Widawsky2015-07-161-11/+10
* i965: Push miptree tiling request into flagsBen Widawsky2015-07-161-10/+11
* i965: Make a helper function intel_miptree_can_use_tr_mode()Anuj Phogat2015-06-291-11/+19
* i965: Make a helper function intel_miptree_release_levels()Anuj Phogat2015-06-291-6/+12
* i965/gen9: Plugin the code for selecting YF/YS tiling on skl+Anuj Phogat2015-06-291-17/+79
* i965: Make a helper function intel_miptree_set_alignment()Anuj Phogat2015-06-291-7/+14
* i965/skl: Fix aligning mt->total_width to the block sizeNeil Roberts2015-06-261-3/+2
* i965: Rename use_linear_1d_layout() and make it globalAnuj Phogat2015-06-161-5/+5
* i965/gen8: Correct HALIGN for AUX surfacesBen Widawsky2015-06-121-5/+8
* i965: Consolidate certain miptree params to flagsBen Widawsky2015-06-121-3/+3
* i965: Make a helper function intel_miptree_set_total_width_height()Anuj Phogat2015-06-081-43/+50
* i965/gen9: Set vertical alignment for the miptreeAnuj Phogat2015-06-081-0/+70
* i965/gen9: Set horizontal alignment for the miptreeAnuj Phogat2015-06-081-0/+81
* i965/gen9: Set tiled resource mode for the miptreeAnuj Phogat2015-06-081-0/+2
* i965: Pass miptree pointer as function parameter in intel_vertical_texture_al...Anuj Phogat2015-06-081-9/+7
* i965: Move intel_miptree_choose_tiling() to brw_tex_layout.cAnuj Phogat2015-06-081-4/+103
* i965: Choose tiling in brw_miptree_layout() functionAnuj Phogat2015-06-081-1/+15
* i965/skl: Align compressed textures to four times the block sizeNeil Roberts2015-05-051-4/+27
* Fix a few typosZoë Blade2015-04-271-1/+1
* i965: Add helper functions to calculate the slice pitch of an array or 3D mip...Francisco Jerez2015-04-271-40/+66
* i965/skl: Fix the qpitch valueNeil Roberts2015-04-201-10/+52
* i965: replace __FUNCTION__ with __func__Marius Predut2015-04-141-1/+1
* i965/skl: Avoid using the 1D stencil layout for stencil-only imagesNeil Roberts2015-03-311-1/+2
* i965/skl: Lay out a 1D miptree horizontallyNeil Roberts2015-03-021-2/+60
* i965/skl: Lay out 3D textures the same as array texturesNeil Roberts2015-03-021-2/+8
* i965/gen8: Use HALIGN_16 if MCS is enabled for non-MSRTAnuj Phogat2015-02-251-0/+3
* i965: Pass pointer to miptree as function parameter in intel_horizontal_textu...Anuj Phogat2015-02-251-6/+6
* i965/gen6: Force tile alignment for each stencil/hiz LODJordan Justen2014-08-151-3/+36
* i965: Support array_layout == ALL_SLICES_AT_EACH_LOD for multiple LODsJordan Justen2014-08-151-2/+19
* i965: Change mipmap array_spacing_lod0 to array_layout (enum)Jordan Justen2014-08-151-1/+1
* i965: Drop mt->levels[].width/height.Eric Anholt2014-02-181-3/+2
* mesa: Change many Type A MESA_FORMATs to meet naming standardMark Mueller2014-01-271-3/+3
* mesa: change gl_format to mesa_formatMark Mueller2014-01-271-2/+2
* i965: Don't store qpitch / 4 as mt->qpitch for compressed surfaces.Kenneth Graunke2014-01-251-4/+4
* s/Tungsten Graphics/VMware/José Fonseca2014-01-171-3/+3
* i965: Store QPitch in intel_mipmap_tree.Kenneth Graunke2013-12-201-6/+5
* i965: Set vertical alignment unit to 4 on Broadwell.Kenneth Graunke2013-12-021-0/+6
* i965/gen7: Prefer vertical alignment of 4 when possible.Paul Berry2013-11-191-3/+22
* i965: Fix vertical alignment for multisampled buffers.Paul Berry2013-11-151-4/+7
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