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path: root/src/mesa/drivers/dri/i965/brw_structs.h
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* i965: Set the destination horiz stride even for da16, as SNB seems to need it.Zhenyu Wang2010-08-201-2/+2
* i965: Add AccWrCtl support on Sandybridge.Zhenyu Wang2010-08-201-2/+3
* i965: Add disasm for SEND mlen/rlen on Sandybridge.Eric Anholt2010-07-081-2/+3
* i965: Add definitions for Sandybridge DP write/read messages.Zhenyu Wang2010-07-081-0/+28
* i965: Fix the name of aa_coverage_slope in the improved AA line params.Eric Anholt2010-06-181-1/+1
* intel: Clean up chipset name and gen num for IronlakeZhenyu Wang2010-04-211-9/+9
* i965: Add Sandybridge viewport setup.Eric Anholt2010-02-251-0/+9
* i965: Add Sandybridge scissor state.Eric Anholt2010-02-251-0/+5
* i965: Start adding support for the Sandybridge CC unit.Eric Anholt2010-02-251-2/+98
* i965: CS FENCE in URB_FENCE is 11-bits wideXiang, Haihao2009-09-021-2/+2
* i965: Spell "conditional" correctly.Eric Anholt2009-08-041-1/+1
* i965: Hook up the disassembler for INTEL_DEBUG={wm,vs}.Eric Anholt2009-08-041-5/+8
* i965: add support for new chipsetsXiang, Haihao2009-07-131-1/+113
* i965: move BRW_MAX_GRF, define BRW_MAX_MRFBrian Paul2009-06-301-0/+8
* i965: Fall back or appropriately adjust offsets of drawing to tiled regions.Eric Anholt2009-06-171-1/+1
* i965: Rename CMD_CONST_BUFFER_STATE to the CS_URB_STATE used in the docs.Eric Anholt2009-02-251-1/+1
* i965: minor commentsBrian Paul2009-01-281-2/+2
* i965: Merge GM45 into the G4X chipset define.Eric Anholt2008-11-021-2/+2
* i965: official name for GM45 chipsetXiang, Haihao2008-07-081-2/+2
* i965: new integrated graphics chipset supportXiang, Haihao2008-01-291-21/+126
* [965] Simplify scissor handling by using DrawBuffer values.Eric Anholt2007-12-171-0/+1
* [965] Replace the state cache suballocator with direct dri_bufmgr use.Eric Anholt2007-12-141-9/+9
* i965: Avoid branch instructions while in single program flow mode.Eric Anholt2007-01-061-3/+19
* Add Intel i965G/Q DRI driver.Eric Anholt2006-08-091-0/+1330
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