aboutsummaryrefslogtreecommitdiffstats
path: root/src/mesa/drivers/dri/i965/brw_sf.c
Commit message (Collapse)AuthorAgeFilesLines
* i965: Move program compile to emit() time.Eric Anholt2011-10-291-2/+3
| | | | | | | Only 4 other prepare() functions are left, which don't rely on this. Reviewed-by: Kenneth Graunke <[email protected]> Acked-by: Paul Berry <[email protected]>
* intel: Convert from GLboolean to 'bool' from stdbool.h.Kenneth Graunke2011-10-181-4/+4
| | | | | | | | | | | | | | | | | I initially produced the patch using this bash command: for file in {intel,i915,i965}/*.{c,cpp,h}; do [ ! -h $file ] && sed -i 's/GLboolean/bool/g' $file && sed -i 's/GL_TRUE/true/g' $file && sed -i 's/GL_FALSE/false/g' $file; done Then I manually added #include <stdbool.h> to fix compilation errors, and converted a few functions back to GLboolean that were used in core Mesa's function pointer table to avoid "incompatible pointer" warnings. Finally, I cleaned up some whitespace issues introduced by the change. Signed-off-by: Kenneth Graunke <[email protected]> Acked-by: Chad Versace <[email protected]> Acked-by: Paul Berry <[email protected]>
* i965: Make brw_compute_vue_map's userclip dependency a boolean.Paul Berry2011-10-061-2/+2
| | | | | | | | | | | | | Previously, brw_compute_vue_map required an argument indicating the number of clip planes in use, but all it did with it was check if it was nonzero. This patch changes brw_compute_vue_map to take a boolean instead. This allows us to avoid some unnecessary recompilation of the Gen4/5 GS and SF threads. Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* mesa: Create _mesa_bitcount_64() to replace i965's brw_count_bits()Paul Berry2011-10-061-1/+1
| | | | | | | | | | | | | | | | The i965 driver already had a function to count bits in a 64-bit uint (brw_count_bits()), but it was buggy (it only counted the bottom 32 bits) and it was clumsy (it had a strange and broken fallback for non-GCC-like compilers, which fortunately was never used). Since Mesa already has a _mesa_bitcount() function, it seems better to just create a _mesa_bitcount_64() function rather than special-case this in the i965 driver. This patch creates the new _mesa_bitcount_64() function and rewrites all of the old brw_count_bits() calls to refer to it. Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Remove two_side_color from brw_compute_vue_map().Paul Berry2011-09-061-2/+1
| | | | | | | | | | | Since we now lay out the VUE the same way regardless of whether two-sided color is enabled, brw_compute_vue_map() no longer needs to know whether two-sided color is enabled. This allows the two-sided color flag to be removed from the clip, GS, and VS keys, so that fewer GPU programs need to be recompiled when turning two-sided color on and off. Reviewed-by: Eric Anholt <[email protected]>
* i965: SF: Remove unnecessary variables.Paul Berry2011-09-061-4/+2
| | | | | | | | | | This patch removes the variables nr_attrs and nr_setup_attrs, whose purpose is now being served by the VUE map. nr_attr_regs and nr_setup_regs are still needed, however they are now computed using the VUE map rather than by counting the number of vertex shader outputs (which caused subtle bugs when gl_PointSize was written). Reviewed-by: Eric Anholt <[email protected]>
* i965: SF: Remove attr_to_idx and idx_to_attr.Paul Berry2011-09-061-11/+1
| | | | | | | | These data structures were serving the same purpose as the VUE map, but were buggy. Now that the code has been transitioned to use the VUE map, they are not needed. Reviewed-by: Eric Anholt <[email protected]>
* i965: SF: Modify calculate_point_sprite_mask to use the VUE map.Paul Berry2011-09-061-1/+7
| | | | Reviewed-by: Eric Anholt <[email protected]>
* i965: Fix Android build by removing relative includesChad Versace2011-08-301-1/+1
| | | | | | | | | | Replace each occurence of #include "../glsl/*.h" with #include "glsl/*.h" Reviewed-by: Ian Romanick <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* i965: Use state streaming on programs, and state base address on gen5+.Eric Anholt2011-06-181-13/+9
| | | | | | | | | | There will be a little bit of thrashing of the program cache BO as the cache warms up, but once the application is in steady state, this reduces relocations on gen5 and later. On my T420 laptop, cairogl firefox-talos-gfx performance improves 2.6% +/- 1.3% (n=6). No statistically significant performance difference on nexuiz (n=5).
* i965: Remove linear_color for GL_PERSPECTIVE_CORRECTION_HINT.Eric Anholt2011-05-261-3/+0
| | | | | | | | | | From the GL 2.1 spec: "Required perspective-correct interpolation for all fragment attributes except depth in sections 3.4.1 and 3.5.1, effectively making GL PERSPECTIVE CORRECT HINT a no-op." Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Get a ralloc context into brw_compile.Kenneth Graunke2011-05-171-1/+6
| | | | | | | | | | | | This would be so much easier if we were using C++; we could simply use constructors and destructors. Instead, we have to update all the callers. While we're at it, ralloc various brw_wm_compile fields rather than explicitly calloc/free'ing them. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Remove dead entrypoints to state cache, rename the one that's left.Eric Anholt2011-04-291-8/+5
| | | | | | | | | | As we expanded the usage of the state cache, it grew extra functionality. However, with the recent state streaming rework, we're back to the state cache being used only for shader kernels, which is the piece of GPU state that's actually expensive to compute again from scratch, since it involves compiling. Reviewed-by: Kenneth Graunke <[email protected]>
* intel: Annotate debug printout checks with unlikely().Eric Anholt2010-11-031-1/+1
| | | | | | | This provides the optimizer with hints about code hotness, which we're quite certain about for debug printouts (or, rather, while we developers often hit the checks for debug printouts, we don't care about performance while doing so).
* Drop GLcontext typedef and use struct gl_context insteadKristian Høgsberg2010-10-131-1/+1
|
* intel: Change dri_bo_* to drm_intel_bo* to consistently use new API.Eric Anholt2010-06-081-2/+2
| | | | | The slightly less mechanical change of converting the emit_reloc calls will follow.
* i965: Fix point coordinate replacement after airlied's ffvertex changes.Eric Anholt2010-05-171-0/+1
| | | | | | | | This basically restores the previous state, where a vertex result slot is set up for the texcoord to be replaced with point coord. Fixes piglit point-sprite test. Bug #27625
* i965: Add SF program disasm under INTEL_DEBUG=sf.Eric Anholt2010-05-171-0/+9
|
* i965: Fix up the handling of point sprite coordinate replacement.Eric Anholt2010-03-081-10/+11
| | | | | | | | | | | | | The code was walking over the regs of pairs of attributes and checking whether the attribute with a given reg index had point sprite enabled. So the point sprite setup code was rarely even getting executed. Instead, we need to determine which channels of a reg need point sprite coordinate replacement. In addition, it was multiplying the attribute by 1/w, when it's supposed to cover (0, 1) in each direction regardless of w, and it wasn't filling in the Z and W components of the texcoord as specified. Fixes piglit point-sprite and the spriteblast demo. Bug #24431, #22245.
* i965: Allow for variable-sized auxdata in the state cache.Eric Anholt2010-01-191-6/+7
| | | | | | Everything has been constant-sized until now, but constant buffer handling changes will make us want some additional variable sized array.
* Merge branch 'outputswritten64'Ian Romanick2009-11-171-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | Add a GLbitfield64 type and several macros to operate on 64-bit fields. The OutputsWritten field of gl_program is changed to use that type. This results in a fair amount of fallout in drivers that use programs. No changes are strictly necessary at this point as all bits used are below the 32-bit boundary. Fairly soon several bits will be added for clip distances written by a vertex shader. This will cause several bits used for varyings to be pushed above the 32-bit boundary. This will affect any drivers that support GLSL. At this point, only the i965 driver has been modified to support this eventuality. I did this as a "squash" merge. There were several places through the outputswritten64 branch where things were broken. I foresee this causing difficulties later for bisecting. The history is still available in the branch. Conflicts: src/mesa/drivers/dri/i965/brw_wm.h
* i965: make brw_sf_prog_key::sprite_origin_lower_left one bitBrian Paul2009-10-291-1/+1
| | | | | Shrinks size of key to 8 bytes from 12. Note that progs/demos/spriteblast.c is still broken.
* i965: interpolate colors with perspective correction by defaultBrian Paul2009-06-121-1/+4
| | | | | | | ...rather than with linear interpolation. Modern hardware should use perspective-corrected interpolation for colors (as for texcoords). glHint(GL_PERSPECTIVE_CORRECTION_HINT, mode) can be used to get linear interpolation if mode = GL_FASTEST.
* i965: fix polygon face orientation when rendering to FBORobert Ellison2009-03-111-2/+8
| | | | | | | | | | | | | | In the i965, the FBO coordinate system is inverted from the standard OpenGL/Mesa coordinate system; that means that the viewport and the polygon face orientation have to be inverted if rendering to a FBO. The viewport was already being handled correctly; but polygon face was not. This caused a conform failure when rendering to texture with two-sided lighting enabled. This fixes the problem in the i965 driver, and adds to the comment about the gl_framebuffer "Name" field so that this isn't a surprise to other driver writers.
* i965: Remove brw->attribs now that we can just always look in the GLcontext.Eric Anholt2009-02-021-6/+8
|
* i965: fix indentationBrian Paul2009-01-141-5/+6
|
* mesa: added "main/" prefix to includes, remove some -I paths from ↵Brian Paul2008-09-181-3/+3
| | | | Makefile.template
* Revert "Revert "Merge branch 'drm-gem'""Dave Airlie2008-08-241-2/+1
| | | | This reverts commit 7c81124d7c4a4d1da9f48cbf7e82ab1a3a970a7a.
* Revert "Merge branch 'drm-gem'"Dave Airlie2008-08-241-1/+2
| | | | | | | | This reverts commit 53675e5c05c0598b7ea206d5c27dbcae786a2c03. Conflicts: src/mesa/drivers/dri/i965/brw_wm_surface_state.c
* intel-gem: Update to new check_aperture API for classic mode.Eric Anholt2008-08-081-2/+1
| | | | | | To do this, I had to clean up some of 965 state upload stuff. We may end up over-emitting state in the aperture overflow case, but that should be rare, and I'd rather have the simplification of state management.
* i965: initial attempt at fixing the aperture overflowDave Airlie2008-04-181-2/+3
| | | | | | | | | Makes state emission into a 2 phase, prepare sets things up and accounts the size of all referenced buffer objects. The emit stage then actually does the batchbuffer touching for emitting the objects. There is an assert in dri_emit_reloc if a reloc occurs for a buffer that hasn't been accounted yet.
* i965: use setup attributes as inputs when allocating registersXiang, Haihao2008-02-141-2/+0
| | | | for WM payload. fix #10767
* i965: new integrated graphics chipset supportXiang, Haihao2008-01-291-1/+1
|
* i965: allocate GRF registers before building subroutines,Xiang, Haihao2007-12-191-4/+4
| | | | it ensures there are sufficient registers for all subroutines.
* [965] Replace the state cache suballocator with direct dri_bufmgr use.Eric Anholt2007-12-141-20/+13
| | | | | | | | | | | | | | | | | | | | | | | The user-space suballocator that was used avoided relocation computations by using the general and surface state base registers and allocating those types of buffers out of pools built on top of single buffer objects. It also avoided calls into the buffer manager for these small state allocations, since only one buffer object was being used. However, the buffer allocation cost appears to be low, and with relocation caching, computing relocations for buffers is essentially free. Additionally, implementing the suballocator required a don't-fence-subdata flag to disable waiting on buffer maps so that writing new data didn't block on rendering using old data, and careful handling when mapping to update old data (which we need to do for unavoidable relocations with FBOs). More importantly, when the suballocator filled, it had no replacement algorithm and just threw out all of the contents and forced them to be recomputed, which is a significant cost. This is the first step, which just changes the buffer type, but doesn't yet improve the hash table to not result in full recompute on overflow. Because the buffers are all allocated out of the general buffer allocator, we can no longer use the general/surface state bases to avoid relocations, and they are set to 0 instead.
* Revert "[965] Add missing flagging of new stage programs for updating stage ↵Eric Anholt2007-12-051-19/+13
| | | | | | | | | state." I had forgotten part of brw_state_cache.c that made this fix not relevant for master (last_addr comparison and flagging based on cache id). This reverts commit a4642f3d18bdaebaba31e5dee72fe5de9d890ffb.
* [965] Add missing flagging of new stage programs for updating stage state.Eric Anholt2007-12-051-13/+19
| | | | | | Otherwise, choosing a new program wouldn't necessarily update the state, and and an old program could be executed, leading to various sorts of pretty pictures or hangs.
* i965: revert commit 1a15b2169ba6cb100627eb525a20a00537cfb6f0,Xiang, Haihao2007-09-121-1/+1
| | | | | | and keep the instruction state unchanged after calling brw_emit_tri_setup/brw_emit_line_setup when building setup thread for SF_UNFILLED_TRIS.
* i965: only take non-varying attribute into account whenXiang, Haihao2007-09-051-1/+1
| | | | | compiling sf_prog. fix bug#11378 (which is introduced by commit d619cceea47dc3070ebb7f7ea4f8b6b31a672d38)
* ARB sprite point support on i965Zou Nan hai2007-07-301-3/+12
|
* Add Intel i965G/Q DRI driver.Eric Anholt2006-08-091-0/+188
This driver comes from Tungsten Graphics, with a few further modifications by Intel.
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-11 19:41:57 +0000