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path: root/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
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* i965: Introduce downcast helpers for prog_data structures.Kenneth Graunke2016-10-051-4/+3
* i965/ir: Pass identity mask to brw_find_live_channel() in the packed dispatch...Francisco Jerez2016-09-211-1/+4
* i965/fs: Take Dispatch/Vector mask into account in FIND_LIVE_CHANNELJason Ekstrand2016-09-211-2/+5
* i965/fs: Handle arbitrary offsets in brw_reg_from_fs_reg for MRF/VGRF registers.Francisco Jerez2016-09-141-3/+2
* i965/fs: Replace fs_inst::regs_written with ::size_written field in bytes.Francisco Jerez2016-09-141-6/+10
* i965/fs: Replace fs_reg::subreg_offset with fs_reg::offset expressed in bytes.Francisco Jerez2016-09-141-2/+2
* i965/fs: Replace fs_reg::reg_offset with fs_reg::offset expressed in bytes.Francisco Jerez2016-09-141-1/+1
* i965: Pass start_offset to brw_set_uip_jip().Matt Turner2016-08-311-1/+1
* i965/fs: Define framebuffer read virtual opcode.Francisco Jerez2016-08-251-0/+20
* i965/fs: Drop bogus writemasking disable bit from HALT instructions.Francisco Jerez2016-08-181-4/+0
* i965: Delete the FS_OPCODE_INTERPOLATE_AT_CENTROID virtual opcode.Kenneth Graunke2016-07-201-5/+0
* i965: Use LZD to implement nir_op_ufind_msbIan Romanick2016-07-191-0/+3
* i965: enable the emission of the DIM instructionSamuel Iglesias Gonsálvez2016-07-141-0/+7
* i965/fs: do not require force_writemask_all with exec_size 4Samuel Iglesias Gonsálvez2016-07-131-1/+1
* i965: Defeat the register stride checker in pull uniform messages.Samuel Iglesias Gonsálvez2016-06-131-1/+1
* i965: Defeat the register stride checker in URB reads.Kenneth Graunke2016-06-131-1/+1
* i965/fs: Add (sub)reg_offset asserts to brw_reg_from_fs_reg.Francisco Jerez2016-05-271-0/+2
* i965/fs: Expose arbitrary channel execution groups to the IR.Francisco Jerez2016-05-271-3/+4
* i965/ir: Make BROADCAST emit an unmasked single-channel move.Francisco Jerez2016-05-271-0/+1
* i965/fs: Lower 32-wide scratch writes in the generator.Francisco Jerez2016-05-271-6/+24
* i965/fs: Implement scratch reads and writes of 4 GRFs at a time.Francisco Jerez2016-05-271-0/+4
* i965/fs: Clean up remaining uses of dispatch_width in the generator.Francisco Jerez2016-05-271-6/+7
* i965/eu: Remove brw_codegen::compressed and ::compressed_stack.Francisco Jerez2016-05-271-5/+5
* i965/fs: No need to reset predicate control after emitting some instructions.Francisco Jerez2016-05-271-2/+0
* i965/fs: Pass current execution size to brw_IF() and brw_DO().Francisco Jerez2016-05-271-2/+2
* i965/fs: Extend region width calculation to allow arbitrary execution sizes.Francisco Jerez2016-05-271-16/+23
* i965/fs: Pass the compression mode to brw_reg_from_fs_reg().Kenneth Graunke2016-05-271-5/+6
* i965/fs: Simplify per-instruction compression control setup in generator.Francisco Jerez2016-05-271-27/+17
* i965/fs: No need to set compression control at the top of generate_code().Francisco Jerez2016-05-271-2/+0
* i965/eu: Fix a bunch of compression control bugs in the generator.Francisco Jerez2016-05-271-1/+1
* i965/fs: Remove FS_OPCODE_PACK_STENCIL_REF virtual instruction.Francisco Jerez2016-05-271-45/+0
* i965/fs: Remove extract virtual opcodes.Francisco Jerez2016-05-271-22/+0
* i965/fs: Remove manual splitting of DDY ops in the generator.Francisco Jerez2016-05-271-37/+1
* i965/fs: Remove manual unrolling of BFI instructions from the generator.Francisco Jerez2016-05-271-34/+2
* i965/fs: Drop Gen7 CMP SIMD unrolling workaround from the generator.Francisco Jerez2016-05-271-36/+10
* i965/fs: Drop lowering code for a few three-source instructions from the gene...Francisco Jerez2016-05-271-47/+4
* i965/fs: Set default access mode to Align1 for all instructions in the genera...Francisco Jerez2016-05-271-0/+1
* i965/fs: Remove handcrafted math SIMD lowering from the generator.Francisco Jerez2016-05-271-91/+21
* i965/fs: Rename Gen4 physical varying pull constant load opcode.Francisco Jerez2016-05-271-5/+5
* i965/fs: Hide varying pull constant load message setup behind logical opcode.Francisco Jerez2016-05-271-7/+2
* i965/fs: Mark UBO uniform pull constant loads as force_writemask_all.Francisco Jerez2016-05-231-0/+2
* i965: Delete dead dFdy flipping code.Kenneth Graunke2016-05-201-19/+5
* i965, anv: Use NIR FragCoord re-center and y-transform passes.Kenneth Graunke2016-05-201-4/+4
* i965: Add infrastucture for sample lod-zero operations.Matt Turner2016-05-191-0/+14
* i965: Make brw_reg_from_fs_reg() halve exec_size when compressed.Kenneth Graunke2016-05-171-4/+6
* i965: Move compression decisions before brw_reg_from_fs_reg().Kenneth Graunke2016-05-171-26/+26
* i965/blorp: Delete the old blorp shader emit codeJason Ekstrand2016-05-141-21/+0
* i965: Fix undefined df bits in brw_reg comparisons.Kenneth Graunke2016-05-141-1/+1
* i965/fs: extend exec_size halving in the generatorConnor Abbott2016-05-101-6/+10
* i965/fs: Don't follow pow with an instruction with two dest regs.Matt Turner2016-05-051-0/+18
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