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path: root/src/mesa/drivers/dri/i965/brw_eu_emit.c
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* i965/gen4-5: Set ENDIF dst and src0 fields to the null register.Francisco Jerez2015-07-071-2/+2
* i965: Add brw_barrier to emit a Gateway Barrier SENDJordan Justen2015-06-121-0/+30
* i965: Add brw_WAIT to emit wait instructionJordan Justen2015-06-121-0/+21
* i965: Silence warning in 3-src type-setting.Matt Turner2015-05-281-0/+2
* i965: Introduce the FIND_LIVE_CHANNEL pseudo-opcode.Francisco Jerez2015-05-041-0/+72
* i965: Introduce the BROADCAST pseudo-opcode.Francisco Jerez2015-05-041-0/+75
* i965: Add memory fence opcode.Francisco Jerez2015-05-041-0/+70
* i965: Add typed surface access opcodes.Francisco Jerez2015-05-041-0/+169
* i965: Add untyped surface write opcode.Francisco Jerez2015-05-041-0/+51
* i965: Fix the untyped surface opcodes to deal with indirect surface access.Francisco Jerez2015-05-041-73/+90
* Fix a few typosZoë Blade2015-04-271-2/+2
* i965: Rename brw_compile to brw_codegenJason Ekstrand2015-04-221-72/+72
* i965: Remove the context field from brw_compilerJason Ekstrand2015-04-221-4/+4
* i965: Make the brw_inst helpers take a device_info instead of a contextJason Ekstrand2015-04-221-498/+500
* i965/fs: Manually set source regioning on PLN instructions.Matt Turner2015-04-211-1/+13
* i965/fs: Allow an execution size of 32.Matt Turner2015-04-211-1/+1
* i965: Replace guess_execution_size with something simpler.Matt Turner2015-04-211-23/+9
* i965: Mask out unused Align16 components in brw_untyped_atomic.Francisco Jerez2015-03-201-2/+11
* i965: Pass number of components explicitly to brw_untyped_atomic and _surface...Francisco Jerez2015-03-201-6/+24
* i965: Factor out logic to build a send message instruction with indirect desc...Francisco Jerez2015-03-201-15/+43
* i965: Emit IF/ELSE/ENDIF/WHILE JIP with type W on Gen7Antia Puentes2015-03-161-4/+4
* i965/fs: Implement SIMD16 dual source blending.Iago Toral Quiroga2015-03-091-1/+2
* i965: replace Elements() with ARRAY_SIZE()Brian Paul2015-03-021-4/+4
* i965: Handle F16TO32/F32TO16 with dword src/dst consistently on both back-ends.Francisco Jerez2015-02-191-2/+12
* i965/gen8: Fix F32TO16 in vec4 mode if the source and destination registers a...Francisco Jerez2015-02-191-9/+27
* i965: Remove now unnecessary Gen8 CMP destination type override.Matt Turner2015-02-041-8/+0
* i965/emit: Assert that src1 is not an MRF after doing the MRF->GRF conversionJason Ekstrand2015-01-221-1/+1
* i965/emit: Do the sampler index adjustment directly in header.0.3Jason Ekstrand2015-01-221-3/+2
* i965: Extract scalar region checking logicBen Widawsky2015-01-201-3/+1
* i965: Make validate_reg tables constantJuha-Pekka Heikkila2014-12-161-4/+4
* i965: Set the region of LINE's src0 to <0,1,0>.Matt Turner2014-12-051-1/+10
* i965: Remove non-existent vertical strides from array.Matt Turner2014-11-061-1/+1
* i965: Fix sampler state pointer adjustment for nonconst samplersChris Forbes2014-11-051-1/+1
* i965: Use the spill destination for the message header on GEN >= 7Jason Ekstrand2014-10-271-6/+13
* Revert "i965: Emit ELSE/ENDIF JIP with type D on Gen 7."Matt Turner2014-10-031-2/+2
* i965/fs: Add a an optional source to the FS_OPCODE_FB_WRITE instructionJason Ekstrand2014-09-301-5/+7
* i965/fs: Use the GRF for UNTYPED_ATOMIC instructionsJason Ekstrand2014-09-301-2/+2
* i965: Use BRW_MATH_DATA_SCALAR when source regioning is scalar.Matt Turner2014-09-291-1/+8
* i965: Emit ELSE/ENDIF JIP with type D on Gen 7.Matt Turner2014-09-251-2/+2
* i965: Set JumpCount, not JIP, on ENDIF on Gen 6.Matt Turner2014-09-251-4/+7
* i965: Generalize sampler state pointer mangling for non-constChris Forbes2014-08-151-1/+13
* i965: Extract helper function for surface state pointer adjustmentChris Forbes2014-08-151-0/+35
* i965: Adjust set_message_descriptor to handle non-sendsChris Forbes2014-08-151-1/+13
* i965: Add low-level support for indirect sendsChris Forbes2014-08-151-0/+15
* Revert "i965/vec4: Use MOV, not OR, to set URB write channel mask bits."Kenneth Graunke2014-08-141-2/+4
* i965/eu: Set src0 file to IMM on Gen8+ flow control instructions.Kenneth Graunke2014-08-121-9/+36
* i965/eu: Refactor brw_WHILE to share a bit more code on Gen6+.Kenneth Graunke2014-08-121-16/+12
* i965/eu: Emulate F32TO16 and F16TO32 on Broadwell.Kenneth Graunke2014-08-121-2/+50
* i965/vec4: Use MOV, not OR, to set URB write channel mask bits.Kenneth Graunke2014-08-121-4/+2
* i965/eu: Allow math on immediates on Broadwell.Kenneth Graunke2014-08-101-3/+6
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