| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | i965: Add gen6 disassembly for DP render cache messages. | Eric Anholt | 2011-08-16 | 1 | -3/+46 |
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| * | i965: Rename dp_render_target struct to gen6_dp. | Kenneth Graunke | 2011-05-13 | 1 | -12/+12 |
| | | | | | | | | | | This is actually just the message descriptor for Gen6+ dataport access; it has nothing to do with the render cache. Access to the sampler cache and constant cache also would use this struct; rename for clarity. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> | ||||
| * | i965: Correct the dp_read message descriptor setup on g4x. | Eric Anholt | 2010-12-23 | 1 | -1/+1 |
| | | | | | | | | It's mostly like gen4 message descriptor setup, except that the sizes of type/control changed to be like gen5. Fixes 21 piglit cases on gm45, including the regressions in bug #32311 from increased VS constant buffer usage. | ||||
| * | i965: Dump the WHILE jump distance on gen6. | Eric Anholt | 2010-12-01 | 1 | -1/+2 |
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| * | i965: Add disasm for the flag register. | Eric Anholt | 2010-10-26 | 1 | -0/+3 |
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| * | i965: Use SENDC on the first render target write on gen6. | Eric Anholt | 2010-10-26 | 1 | -3/+7 |
| | | | | | | | This is apparently required, as the thread will be initiated while it still has dependencies, and this is what waits for those to be resolved before writing color. | ||||
| * | i965: Add some clarification of the WECtrl field. | Eric Anholt | 2010-10-06 | 1 | -2/+2 |
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| * | i965: Fix up IF/ELSE/ENDIF for gen6. | Eric Anholt | 2010-10-06 | 1 | -0/+5 |
| | | | | | | | The jump delta is now in the part of the instruction where the destination fields used to be, and the src args are ignored (or not, for the new non-predicated IF that we don't use yet). | ||||
| * | i965: In disasm, gen6 fb writes don't put msg reg # in destreg_conditionalmod. | Eric Anholt | 2010-10-04 | 1 | -1/+1 |
| | | | | | It instead sensibly appears in the src0 slot. | ||||
| * | i965: disasm quarter and write enable instruction control on sandybridge | Zhenyu Wang | 2010-09-28 | 1 | -9/+61 |
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| * | i965: Add disasm for gen5 sampler messages. | Eric Anholt | 2010-08-28 | 1 | -6/+19 |
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| * | i965: Add AccWrCtl support on Sandybridge. | Zhenyu Wang | 2010-08-20 | 1 | -0/+7 |
| | | | | | Whenever the accumulator results are needed, this bit must be set. | ||||
| * | i965: Mention the mlen and rlen for URB reads. | Zhenyu Wang | 2010-08-20 | 1 | -0/+5 |
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| * | i965: Adjust disasm of subreg numbers to be in units of the register type. | Zhenyu Wang | 2010-08-20 | 1 | -6/+20 |
| | | | | | | This makes reading the code easier when matching up to the specs, which also use this format. | ||||
| * | i965: Add disasm for Compr4 instruction compression. | Eric Anholt | 2010-08-16 | 1 | -1/+16 |
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| * | i965: Fix the disasm output for da16 src widths. | Eric Anholt | 2010-07-22 | 1 | -1/+1 |
| | | | | | | | This has confused me twice now. It's a fixed width of 4 (usually a region description of <4,4,1>), not 1. If it was 1, we'd have been skipping all over register space. | ||||
| * | i965: Add disasm for dataport reads (register unspilling). | Eric Anholt | 2010-07-21 | 1 | -1/+22 |
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| * | i965: Add disasm for SEND mlen/rlen on Sandybridge. | Eric Anholt | 2010-07-08 | 1 | -1/+1 |
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| * | i965: Fix disasm of a SEND's mlen and rlen on Ironlake. | Eric Anholt | 2010-07-08 | 1 | -4/+11 |
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| * | i965: Add decode for Sandybridge DP write messages. | Zhenyu Wang | 2010-07-08 | 1 | -9/+21 |
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| * | i965: Parse the ff_sync URB send opcode on Ironlake disasm. | Eric Anholt | 2010-05-14 | 1 | -1/+15 |
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| * | i965: Dump out the correct shared function for SEND on Ironlake. | Eric Anholt | 2010-05-14 | 1 | -3/+11 |
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| * | i965: Add disasm for SNB MATH opcode. | Eric Anholt | 2010-03-22 | 1 | -1/+6 |
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| * | i965: Use the PLN instruction when possible in interpolation. | Eric Anholt | 2010-03-10 | 1 | -0/+1 |
| | | | | | | | Saves an instruction in PINTERP, LINTERP, and PIXEL_W from brw_wm_glsl.c For non-GLSL it isn't used yet because the deltas have to be laid out differently. | ||||
| * | i965: Print the offset for IFF in disasm | Eric Anholt | 2010-03-10 | 1 | -1/+1 |
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| * | i965: Print the offsets for WHILE and BREAK in disasm. | Eric Anholt | 2010-03-09 | 1 | -2/+2 |
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| * | Merge branch 'mesa_7_7_branch' | Brian Paul | 2009-12-31 | 1 | -0/+1 |
| |\ | | | | | | | | | | | | | | | Conflicts: configs/darwin src/gallium/auxiliary/util/u_clear.h src/gallium/state_trackers/xorg/xorg_exa_tgsi.c src/mesa/drivers/dri/i965/brw_draw_upload.c | ||||
| | * | i965: Add missing va_end. | Vinson Lee | 2009-12-24 | 1 | -0/+1 |
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| * | | i965: Fix setup of immediate types for gen4 disasm. | Eric Anholt | 2009-12-26 | 1 | -1/+1 |
| |/ | | | | Caught by clang. | ||||
| * | i965: Print out ELSE and ENDIF src1 arguments like IF does. | Eric Anholt | 2009-08-04 | 1 | -2/+2 |
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| * | i965: Hook up the disassembler for INTEL_DEBUG={wm,vs}. | Eric Anholt | 2009-08-04 | 1 | -5/+7 |
| | | | | | | I was getting tired of doing the dance of INTEL_DEBUG=batch, copying it out, and running intel-gen4disasm on it. | ||||
| * | i965: Initial import of disasm code from intel-gen4asm. | Eric Anholt | 2009-08-04 | 1 | -0/+901 |
| There's a bunch of stuff from gen4asm and gpu-tools that we probably want to make into a library instead of cargo-culting it around. | |||||
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