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* i965/disasm: Fix RC message type strings on Gen7+.Francisco Jerez2016-08-251-3/+25
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965: fix compiler warnings for 32bit buildTimothy Arceri2016-07-141-25/+25
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965: Add infrastucture for sample lod-zero operations.Matt Turner2016-05-191-0/+3
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965: add support for disassembling DF immediatesConnor Abbott2016-05-101-1/+1
| | | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* i965/disasm: fix disasm of 3-src doublesConnor Abbott2016-05-101-0/+1
| | | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* i965: Merge inst_info and opcode_desc tables.Matt Turner2016-05-031-74/+0
| | | | | | | I merged opcode_desc into inst_info (instead of the other way around) because inst_info was sorted by opcode number. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/disasm: Wrap opcode_desc look-up in a function.Francisco Jerez2016-05-031-10/+14
| | | | | | | | | | | | | | The function takes a device info struct as argument in addition to the opcode number in order to disambiguate between multiple opcode_desc entries for different instructions with the same opcode number. Reviewed-by: Iago Toral Quiroga <[email protected]> [v1] [v2] mattst88: Put brw_opcode_desc() in brw_eu.c instead of moving it there in a later patch. Reviewed-by: Kenneth Graunke <[email protected]> [v2] [v3] mattst88: Return NULL if opcode >= ARRAY_SIZE(opcode_descs) Reviewed-by: Matt Turner <[email protected]>
* i965/disasm: Decode per-slot offsets.Kenneth Graunke2016-04-091-0/+5
| | | | | | | We just never bothered to decode this. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ben Widawsky <[email protected]>
* i965/disasm: Decode "channel mask present" bit correctly.Kenneth Graunke2016-04-091-4/+15
| | | | | | | | Bit 15 means "interleave" for most messages, but for SIMD8 messages it means "use channel masks". Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ben Widawsky <[email protected]>
* i965/disasm: Simplify the URB opcode printing with ?:.Kenneth Graunke2016-04-091-7/+6
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ben Widawsky <[email protected]>
* i965: Clean up #includes in the compiler.Matt Turner2015-11-241-3/+0
| | | | Reviewed-by: Ian Romanick <[email protected]>
* i965: Use BRW_MRF_COMPR4 macro in more places.Matt Turner2015-11-131-2/+2
| | | | | Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Don't consider control flow instructions to have sources.Matt Turner2015-11-121-8/+8
| | | | | | | | | | | | And why did IFF have a destination? I suspect that once upon a time the disassembler used this information to know which fields to find the jump targets in. The jump targets have moved, so the disassembler has to know how to handle these per-generation anyway. Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Fill out instruction list.Matt Turner2015-11-121-6/+10
| | | | | | | | | | | Add some instructions: illegal, movi, sends, sendsc. Remove some instructions with reused opcodes: msave, mrestore, push, pop, goto. I did have some gross code for disassembling opcodes per-generation, but there's very little meaningful overlap so it's probably not needed. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs/skl+: Use ld2dms_w instead of ld2dmsNeil Roberts2015-11-051-0/+1
| | | | | | | | | | | | In order to support 16x MSAA, skl+ has a wider version of ld2dms that takes two parameters for the MCS data. The MCS data retrieved from the ld_mcs instruction already returns 4 or 8 registers and is documented to return zeroes for the mcsh value when the sample count is less than 16. v2: Use get_lowered_simd_width to fall back to SIMD8 instructions when the message length would be too long in SIMD16. Reviewed-by: Ben Widawsky <[email protected]>
* i965: Print the type and writemask on null destinations.Matt Turner2015-10-291-1/+1
| | | | | | | | These are often useful in debugging, and the writemask (actually "Channel Enables") determines more than just what goes into the destination. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/disasm: Remove unused _addr_mode argument from src_ia1().Matt Turner2015-10-291-3/+0
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/vec4: print predicate control at brw_vec4 dump_instructionAlejandro Piñeiro2015-10-221-1/+1
| | | | | | | v2: externalize pred_ctrl_align16 from brw_disasm.c instead of adding a copy on brw_vec4.c, as suggested by Matt Turner Reviewed-by: Matt Turner <[email protected]>
* i965: add support for textureSamples functionIlia Mirkin2015-09-101-0/+1
| | | | | | Signed-off-by: Ilia Mirkin <[email protected]> [v2: kayden-supplied code in fs_nir replacing need for logical opcode] Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Add defines for all new Gen7/8 URB opcodesChris Forbes2015-09-081-9/+9
| | | | | | | Tessellation needs to emit URB reads and atomics; Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Improve disassembly of data port read messages.Kenneth Graunke2015-09-031-4/+27
| | | | | | | | We now print out the name of the message instead of its numerical value, and label the message control and surface numbers. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* i965: Disassemble Gateway SEND messagesJordan Justen2015-06-121-0/+16
| | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* i965/disasm: Skip swizzle disassembly when using 3-src repctrl.Matt Turner2015-05-221-9/+12
| | | | | ... since it's always .x, and also always print the subreg offset when using repctrl.
* i965: Disassemble sampler message names on Gen5+.Kenneth Graunke2015-04-251-4/+34
| | | | | | | | | | | | | | | | | | | | | | Previously, sampler messages were decoded as sampler (1, 0, 2, 2) mlen 6 rlen 8 { align1 1H }; I don't know how much time we've collectly wasted trying to read this format. I can never recall which number is the surface index, sampler index, message type, or...whatever that other number is. Figuring out the message name from the numerical code is also painful. Now they decode as: sampler sample_l SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 8 { align1 1H }; This is easy to read at a glance, and matches the format I used for render target formats. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* i965: Make the disassembler take a device_info instead of a contextJason Ekstrand2015-04-221-86/+76
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965: Make the brw_inst helpers take a device_info instead of a contextJason Ekstrand2015-04-221-231/+241
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/disasm: Print the type after the swizzle also for 3src src operandsVille Syrjälä2015-04-101-3/+3
| | | | | | | | | The disassembly currently has the swizzle after the type for 3src source operands, and the other way around for 2src. Flip the type and swizzle around for 3src so that the output matches 2src. Reviewed-by: Matt Turner <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]>
* i965/disasm: Fix format stringsChris Forbes2015-03-141-24/+24
| | | | | | | | Most of the brw_inst_* api returns 64bit values. This fixes disassembly of sampler messages, etc. Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/disasm: Mark format() as being printf-style.Chris Forbes2015-03-141-0/+3
| | | | | | | | This allows us to get warnings from GCC when we mess up the format strings. Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Add a function to disassemble an instruction from the 4 dwords.Kenneth Graunke2015-02-171-0/+12
| | | | | | | | | I used this a while back when debugging GPU hangs, and it seems like it could be useful, so I figured I'd add it so people can use it in the debugger. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965/disasm: Disassemble tdr and tm registers properly.Matt Turner2014-12-011-0/+6
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Disassemble vector float immediates properly.Matt Turner2014-11-251-1/+5
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* i965/disasm: Fix all32h/any32h predicate disassembly.Matt Turner2014-11-241-1/+1
| | | | Reviewed-by: Chris Forbes <[email protected]>
* i965/disasm: Properly decode branch_ctrl (gen8+)Ben Widawsky2014-11-201-1/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for decoding the new branch control bit. I saw two things wrong with the existing code. 1. It didn't bother trying to decode the bit. - While we do not *intentionally* emit this bit today, I think it's interesting to see if we somehow ended up with the bit set. It may also be useful in the future. 2. It seemed to be the wrong bit. - The docs are pretty poor wrt which bit this actually occupies. To me, it /looks/ like it should be bit 28. I am not sure where Ken got 30 from. I verified it should be 28 by looking at the simulator code. I also added the most basic support for GOTO simply so we don't need to remember to change the function in the future. v2: Move the branch_ctrl check out of the if gen >= 6 check to make it more readable. (Matt) ENDIF doesn't have branch_ctrl (Matt + Ken) Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/disasm: Add missing message type for Gen7 DP untyped surface readChris Forbes2014-10-161-0/+1
| | | | | | | | This is used to implement GLSL's atomicCounter() intrinsic. Previously it *worked*, but the disassembly was bogus. Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* i965: Add BRW_OPCODE_NENOP for G45.Matt Turner2014-09-251-2/+3
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/disasm: Show jump count for if/iff/halt.Matt Turner2014-08-281-1/+1
| | | | | | These instructions don't have pop count. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/disasm: Disassemble JMPI's source properly.Matt Turner2014-08-281-1/+2
| | | | | | | The source can be a register as well as an immediate, and disassembling a register as an immediate can have some strange results. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/disasm: Add break/cont/halt to list of has_uip().Matt Turner2014-08-281-1/+4
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/disasm: Disassemble Z/NZ conditional modifiers as .z/.nz.Matt Turner2014-08-281-2/+2
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/disasm: Add CSEL.Matt Turner2014-08-181-0/+1
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* i965: Don't print WE_normal in disassembly.Kenneth Graunke2014-07-231-1/+1
| | | | | | | | | Dropping this helps most lines fit in an 80 column terminal. The absence of WE_normal also helps call attention to WE_all, where something unusual is going on. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/disasm: Don't disassemble the URB complete field on Broadwell.Kenneth Graunke2014-07-211-2/+4
| | | | | | | | It doesn't exist, so attempting to read it will trigger generation assertions in the brw_inst API. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/disasm: add support for pixel interpolator messagesChris Forbes2014-07-131-0/+17
| | | | | | | V3: Rework for brw_inst changes Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/disasm: Disassemble indirect sends more properlyChris Forbes2014-07-121-162/+174
| | | | | | | | | | | - Don't try to disassemble send's src1 as a descriptor if it's not an immediate. - In the same case, show src1 as an operand (makes it easier to see bogus register regions, etc -- the hardware is very fussy) Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/disasm: Fix disassembly of the any16h/all16h predicates.Kenneth Graunke2014-07-081-1/+1
| | | | | | | | BRW_PREDICATE_ALIGN1_ANY16H was incorrectly being disassembled as "all16h", and ALL16H would probably print as "(null)". Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/disasm: Improve render target write message disassembly.Kenneth Graunke2014-06-301-30/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously, we decoded render target write messages as: render ( RT write, 0, 16, 12, 0) mlen 8 rlen 0 which made you remember (or look up) what the numbers meant: 1. The binding table index 2. The raw message control, undecoded: - Last Render Target Select - Slot Group Select - Message Type (SIMD8, normal SIMD16, SIMD16 replicate data, ...) 3. The dataport message type, again (already decoded as "RT write") 4. The write commit bit (0 or 1) Needless to say, having to decipher that yourself is annoying. Now, we do: render RT write SIMD16 LastRT Surface = 0 mlen 8 rlen 0 with optional "Hi" and "WriteCommit" for slot group/write commit. Thanks to the new brw_inst API, we can also stop duplicating code on a per-generation basis. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965/disasm: Rename msg_target to SFID.Kenneth Graunke2014-06-301-12/+8
| | | | | | | | | | We haven't used the name "message target" in a while - there are a lot of things called "target", and it gets confusing. SFID ("Shared Function ID") is the term commonly used in the modern documentation. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965/disasm: Fix typo in RT UNORM write message.Kenneth Graunke2014-06-301-1/+1
| | | | | | | | | The name of this message is "Render Target UNORM Write" (Sandybridge PRM, Volume 4 Part 1, Page 210). Drop the bogus 'c'. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965/disasm: Use Gen6+ SFID case labels.Kenneth Graunke2014-06-301-2/+4
| | | | | | | | | | Most developers will recognize the Gen6+ SFID names more quickly than the Gen4-5 ones. Given that they're the same values, just use the new names. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
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