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* i965/vs: Add support for pull constant loads for uniform arrays.Eric Anholt2011-08-301-0/+1
| | | | | v2: reworked the instruction emit and made use of gen6_resolve_implied_move, from Ken's review
* i965: Implement textureSize (TXS) on Gen4.Kenneth Graunke2011-08-231-1/+0
| | | | | | | | | | | | | | Also, remove the BRW_SAMPLER_MESSAGE_SIMD8_RESINFO #define because there totally isn't a SIMD8 variant. Unfortunately, resinfo returns FLOAT32 on Broadwater/Crestline, unlike G45 which returns a proper UINT32. This turns out to be simple, however: when we emit MOVs to select the desired half of the SIMD16 result, we can simply override the register type to be float so it's converted to an integer. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965/fs: Implement textureSize (TXS) on Gen5+.Kenneth Graunke2011-08-231-0/+2
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965/vs: Move virtual GRFs with array accesses to them to scratch space.Eric Anholt2011-08-161-0/+2
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* i965: Start adding the VS visitor and codegen.Eric Anholt2011-08-161-0/+2
| | | | | | The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
* i965: Rename math FS_OPCODE_* to SHADER_OPCODE_*.Eric Anholt2011-08-161-8/+8
| | | | I want to just use the same enums in the VS.
* i965: Create a shared enum for hardware and compiler-internal opcodes.Eric Anholt2011-08-161-52/+82
| | | | | This should make gdbing more pleasant, and it might be used in sharing part of the codegen between the VS and FS backends.
* i965: Rename CMD_VF_STATISTICS_(965|GM45) to include "3DSTATE".Kenneth Graunke2011-07-181-2/+2
| | | | | | | | | | Including the full "3DSTATE_VF_STATISTICS" should make it easier to cross-reference the code and documentation. Also, move the 965/GM45 suffix to the beginning for consistency with newer #defines. Signed-off-by: Kenneth Graunke <[email protected]>
* i965: Rename CMD_VERTEX_(BUFFER|ELEMENT) to 3DSTATE_VERTEX_...S.Kenneth Graunke2011-07-181-2/+2
| | | | | | This makes our code use the same names as the documentation. Signed-off-by: Kenneth Graunke <[email protected]>
* i965: Convert system instruction pointer to OUT_BATCH style.Kenneth Graunke2011-07-071-1/+1
| | | | | | | | Also rename it from CMD_STATE_INSN_POINTER to CMD_STATE_SIP to match the documentation. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Switch brw_state_dump to using bitshifting for surface state.Eric Anholt2011-05-311-0/+4
| | | | Reviewed-by: Ian Romanick <[email protected]>
* i965: Replace struct with bit shifting for WM pull constant surfaces.Eric Anholt2011-05-311-0/+1
| | | | | | This reduces compiled size (4.7% of brw_wm_surface_state.o). Reviewed-by: Ian Romanick <[email protected]>
* i965: Replace struct with bit shifting for WM render target surfaces.Eric Anholt2011-05-311-0/+5
| | | | | | This massively reduces compiled size (6.7% of brw_wm_surface_state.o). Reviewed-by: Ian Romanick <[email protected]>
* i965: Add defines for surface state setup using bitfield shifting.Eric Anholt2011-05-311-1/+33
| | | | | | | It turns out that gcc is just awful at generating code for brw_structs.h style state setup, and using bitshifting on u32s generates better code while being similarly readable (and more verifiable compared to the specs, using the INTEL_MASK macro).
* i965: Set Address Modify Enable in VERTEX_BUFFER on Ivybridge.Kenneth Graunke2011-05-171-0/+1
| | | | | | | | Otherwise, Ivybridge seems to ignore the newly supplied data, giving us rubbish for vertices. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Emit 3DPRIMITIVE Ivybridge-style.Kenneth Graunke2011-05-171-0/+3
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Add depth buffer support on Ivybridge.Kenneth Graunke2011-05-171-2/+7
| | | | | | | | This also disables the HiZ and separate stencil buffers. We still need to implement stencil. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Upload sampler state pointers on Ivybridge.Kenneth Graunke2011-05-171-0/+4
| | | | | | | | Since we currently only support sampling in the fragment shader, we only bother to emit the PS variant. In the future we'll need to emit others. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Disable binding table pointers for unused pipeline stages.Kenneth Graunke2011-05-171-0/+2
| | | | | | | This may not be necessary, but it seems like a good idea. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Upload binding table pointers on Ivybridge.Kenneth Graunke2011-05-171-0/+4
| | | | | | | Ivybridge uses per-stage commands to update binding table pointers. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Explicitly disable unused pipeline stages on Ivybridge.Kenneth Graunke2011-05-171-0/+11
| | | | | | | This may not be strictly necessary, but seems wise. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Initial Ivybridge Viewport state setup.Kenneth Graunke2011-05-171-0/+3
| | | | | | | | | | | SF and CLIP viewport state has been combined into SF_CLIP_VIEWPORT; SF_CLIP and CC state pointers can now be uploaded independently. Some portions of the hardware documentation refer to separate upload commands for SF and CLIP; these are outdated and incorrect. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Initial Ivybridge Clip state setup.Kenneth Graunke2011-05-171-0/+9
| | | | | | | | | | | Copied from gen6_clip_state.c. This enables early culling and sets the necessary fields. Otherwise, it is entirely the same, so I doubt this patch is strictly necessary for a functional driver. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Initial Ivybridge CC state setup.Kenneth Graunke2011-05-171-0/+2
| | | | | | | | | The state itself still seems to be the same; the only change is that each part (CC, BLEND, DEPTH_STENCIL) can now be uploaded independently. Thus, we still rely on the code in gen6_cc.c to set up the state. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Initial Ivybridge WM/PS state setup.Kenneth Graunke2011-05-171-0/+71
| | | | | | | | | | Copied from gen6_wm_state.c. The main change from Sandybridge seems to be that 3DSTATE_WM was split into two separate state packet commands: 3DSTATE_WM and 3DSTATE_PS. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Initial Ivybridge SF/SBE state setup.Kenneth Graunke2011-05-171-1/+22
| | | | | | | | | | | | Copied from gen6_sf_state.c. The main change from Sandybridge seems to be that 3DSTATE_SF was split into two separate state packet commands: 3DSTATE_SF and 3DSTATE_SBE ("setup backend"). The bit-offsets are even the same - only the DWords numbers have shuffled around a bit. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Initial Ivybridge URB space partitioning, including push constants.Kenneth Graunke2011-05-171-1/+12
| | | | | | | | | Currently this always reserves 16kB for push constants, regardless of how much space is needed, and partitions it evenly betwen the VS and FS. This is probably not ideal, but is straightforward. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Attempt to un-muddle Gen6 data port message target defines.Kenneth Graunke2011-05-131-3/+6
| | | | | | | | | | | | | | | | These are documented on page 245 of IHD_OS_Vol4_Part2.pdf (the public Sandybridge documentation/SEND instruction description). Somebody had the bright idea to reuse gen4/5 defines labelled READ/WRITE which just happened to be the same values as Render Cache/Sampler Cache. It turns out that this field has nothing to do with READ/WRITE on Sandybridge, but rather represents which data port to direct it to. This was especially confusing in brw_set_dp_read_message, which used "BRW_MESSAGE_TARGET_DATAPORT_WRITE." In a read function. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Fix incorrectly named data port define.Kenneth Graunke2011-05-131-1/+1
| | | | | | | According to my documentation this is actually "Media Block Write" on Gen4-5; there has never been a "DWord Block Write." Signed-off-by: Kenneth Graunke <[email protected]>
* i965: Fix typo in Gen6 "DWord Scattered Write" message define.Kenneth Graunke2011-05-131-1/+1
| | | | | | It's DWORD, not DWORLD. Signed-off-by: Kenneth Graunke <[email protected]>
* i965: Convert 3DPRIMITIVE command from struct-style to OUT_BATCH style.Kenneth Graunke2011-04-181-5/+6
| | | | | | | | | | Most of the newer portions of the code use OUT_BATCH style. I prefer this style because it offers a clear distinction between a) hardware messages/structures with a mandatory format, and b) data structures for our own internal use that we can format however we want. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Define BRW_DEPTHFORMAT_D24_UNORM_X8_UINTChad Versace2011-04-121-0/+1
| | | | | | | This depth format was added in Gen5. Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* i965: Rename BRW_DATAPORT_..._GEN6 messages to GEN6_... for consistency.Kenneth Graunke2011-03-161-8/+8
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* i965: Rename BRW_SAMPLER_MESSAGE_..._GEN5 to GEN5_SAMPLER_MESSAGE.Kenneth Graunke2011-03-161-7/+7
| | | | We already have lots of GEN6_* defines; this seems more consistent.
* i965: Add #defines for gen4 SIMD8 TXB/TXL with shadow comparison.Kenneth Graunke2011-02-251-0/+2
| | | | From volume 4, page 161 of the public i965 documentation.
* i965: Rename a few more commands to match the documentation.Kenneth Graunke2011-02-081-2/+2
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* i965: Add #defines for HiZ and separate stencil buffer commands.Kenneth Graunke2011-01-101-0/+3
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* i965: Rename more #defines to 3DSTATE rather than CMD or CMD_3D.Kenneth Graunke2011-01-101-12/+12
| | | | Again, this makes it match the documentation.
* i965: Remove unused #defines which only contain the sub-opcode.Kenneth Graunke2011-01-101-22/+0
| | | | | | | | | Most _3DSTATE defines contain the command type, sub-type, opcode, and sub-opcode (i.e. 0x7905). These, however, contain only the sub-opcode (i.e. 0x05). Since they are inconsistent with the rest of the code and nothing uses them, simply delete them. The _3DOP and _3DCONTROL defines seemed similar, and were also unused.
* i965: Rename various gen6 #defines to match the documentation.Kenneth Graunke2011-01-061-15/+15
| | | | | | | | This should make it easier to cross-reference the code and hardware documentation, as well as clear up any confusion on whether constants like CMD_3D_WM_STATE mean WM_STATE (pre-gen6) or 3DSTATE_WM (gen6+). This does not rename any pre-gen6 defines.
* i965: Add support for SRGB DXT1 formats.Eric Anholt2011-01-041-0/+1
| | | | | | | | | | This makes fbo-generatemipmap-formats GL_EXT_texture_sRGB-s3tc match fbo-generatemipmap-formats GL_EXT_texture_compression_s3tc and swrast in bad DXT1_RGBA alpha=0 handling, but it means we won't unpack and repack someone's textures into uncompressed SARGB8 format.
* i965: Set the alternative floating point mode on gen6 VS and WM.Eric Anholt2010-12-161-0/+4
| | | | | | | This matches how we did the math instructions pre-gen6, though it applies to non-math as well. Fixes vp1-LIT test 2 (degenerate case: 0 ^ 0 -> 1)
* i965: support for two-sided lighting on SandybridgeXiang, Haihao2010-12-101-0/+7
| | | | | | VS places color attributes together so that SF unit can fetch the right attribute according to object orientation. This fixes light issue in mesa demo geartrain, projtex.
* i965: Add support for the instruction compression bits on gen6.Eric Anholt2010-12-061-0/+7
| | | | | | Since the 8-wide first-quarter and 16-wide first-half have the same bit encoding, we now need to track "do you want instruction compression" in the compile state.
* i965: Add user clip planes support to gen6.Eric Anholt2010-10-281-0/+7
| | | | | Fixes piglit user-clip, and compiz desktop switching when dragging a window and using just 2 desktops. Bug #30446.
* i965: Use SENDC on the first render target write on gen6.Eric Anholt2010-10-261-0/+1
| | | | | | This is apparently required, as the thread will be initiated while it still has dependencies, and this is what waits for those to be resolved before writing color.
* i965: Add some clarification of the WECtrl field.Eric Anholt2010-10-061-2/+19
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* i965: force zero in clipper to ignore RTAIndex on sandybridgeZhenyu Wang2010-09-281-0/+1
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* i965: Add support for texturing with bias to i965 FS backend.Eric Anholt2010-08-301-0/+3
| | | | | Fixes 5 piglit tests for bias. Note that LOD is a 1.30 feature and not yet supported.
* i965: Clean up a few magic numbers to use brw_defines.h defs.Eric Anholt2010-07-261-0/+2
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