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path: root/src/mesa/drivers/dri/i965/brw_defines.h
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* i965: Implement "Static Vertex Count" geometry shader optimization.Kenneth Graunke2015-09-261-0/+5
* i965/fs: Implement FS_OPCODE_GET_BUFFER_SIZESamuel Iglesias Gonsalvez2015-09-251-0/+1
* i965/vec4: Implement VS_OPCODE_GET_BUFFER_SIZESamuel Iglesias Gonsalvez2015-09-251-0/+3
* i965/cs: Implement DispatchComputeIndirect supportJordan Justen2015-09-241-0/+2
* i965: Add defines for tessellation stagesChris Forbes2015-09-221-0/+72
* i965/cs: Enable barrier in MEDIA_INTERFACE_DESCRIPTORJordan Justen2015-09-101-0/+2
* i965: add support for textureSamples functionIlia Mirkin2015-09-101-0/+2
* i965: Mark topologies with adjacency information as G45+.Kenneth Graunke2015-09-081-4/+4
* i965: Fix value of _3DPRIM_TRIFAN_NOSTIPPLE.Kenneth Graunke2015-09-081-1/+1
* i965: Add defines for all new Gen7/8 URB opcodesChris Forbes2015-09-081-1/+7
* i965/gen9: Annotate input coverage mask changeBen Widawsky2015-09-031-0/+16
* i965/cs: Setup push constant data for uniformsJordan Justen2015-09-021-0/+6
* i965/chv|skl: Apply sampler bypass w/aBen Widawsky2015-08-311-0/+1
* i965/surface_formats: add support for 2D ASTC surface formatsNanley Chery2015-08-261-0/+32
* i965/gen7-8: Set up early depth/stencil control appropriately for image load/...Francisco Jerez2015-08-111-0/+3
* i965/gen7-8: Poke the 3DSTATE UAV access enable bits.Francisco Jerez2015-08-111-0/+4
* i965: Define virtual instruction to calculate the high 32 bits of a multiply.Francisco Jerez2015-08-061-0/+5
* i965/fs: Define logical typed and untyped surface opcodes.Francisco Jerez2015-07-291-0/+20
* i965/fs: Define logical texture sampling opcodes.Francisco Jerez2015-07-291-0/+31
* i965/fs: Remove the FS_OPCODE_SET_OMASK pseudo-opcode.Francisco Jerez2015-07-291-1/+0
* i965/fs: Define logical framebuffer write opcode.Francisco Jerez2015-07-291-0/+15
* i965: Define HW-binding table and resource streamer control opcodesAbdiel Janulgue2015-07-181-0/+30
* i965/gen9: Use custom MOCS entries set up by the kernel.Francisco Jerez2015-07-161-5/+6
* i965/cs: Initialize GPGPU Thread CountJordan Justen2015-07-141-0/+5
* i965/skl: Set the pulls bary bit in 3DSTATE_PS_EXTRANeil Roberts2015-07-061-0/+1
* i965/gen9: Don't use encrypted MOCSBen Widawsky2015-06-231-2/+2
* i965/gen9: Disable Mip Tail for YF/YS tiled surfacesAnuj Phogat2015-06-161-0/+3
* i965/gen9: Set tiled resource mode in surface stateAnuj Phogat2015-06-161-0/+6
* i965/fs: Implement support for ir_barrierJordan Justen2015-06-121-0/+5
* i965: Add GATEWAY_SFID definitionsJordan Justen2015-06-121-0/+8
* i965: Create a shader_dispatch_mode enum to replace VS/GS fields.Kenneth Graunke2015-06-011-3/+2
* i965: Add Gen9 surface state decodingBen Widawsky2015-05-181-0/+2
* i965: Add gen8 surface state debug infoBen Widawsky2015-05-181-1/+3
* i965: Add gen7+ sampler state to batch debugBen Widawsky2015-05-181-0/+1
* i965: Use predicate enable bit for conditional rendering w/o stallingNeil Roberts2015-05-121-0/+1
* i965/gen6: setup limits for ARB_viewport_arrayChris Forbes2015-05-061-1/+1
* i965: Introduce the FIND_LIVE_CHANNEL pseudo-opcode.Francisco Jerez2015-05-041-0/+8
* i965: Introduce the BROADCAST pseudo-opcode.Francisco Jerez2015-05-041-0/+6
* i965: Add memory fence opcode.Francisco Jerez2015-05-041-0/+2
* i965: Add typed surface access opcodes.Francisco Jerez2015-05-041-0/+4
* i965: Add untyped surface write opcode.Francisco Jerez2015-05-041-0/+1
* i965/cs: Emit MEDIA_STATE_FLUSH after WALKERJordan Justen2015-05-021-0/+1
* i965/cs: Implement brw_emit_gpgpu_walkerJordan Justen2015-05-021-0/+13
* i965/cs: Upload brw_cs_stateJordan Justen2015-05-021-0/+20
* i965/cs: Add CS_OPCODE_CS_TERMINATEJordan Justen2015-05-021-0/+5
* i965/ps: Use SET_FIELD() for sampler countTopi Pohjolainen2015-04-301-0/+1
* i965/fs: Combine pixel center calculation into one inst.Matt Turner2015-04-211-0/+2
* i965/fs: Emit ADDs for gl_FragCoord, not virtual opcodes.Matt Turner2015-04-211-2/+0
* i965/skl: Add the header for constant loads outside of the generatorNeil Roberts2015-04-161-0/+1
* i965: Add missing defines for render cache messages.Francisco Jerez2015-03-021-1/+7
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