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path: root/src/mesa/drivers/dri/i965/brw_defines.h
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* i965/fs: Remove the FS_OPCODE_SET_SIMD4X2_OFFSET virtual opcode.Francisco Jerez2016-12-141-1/+0
* i965: Factor out oword block read and write message control calculation.Francisco Jerez2016-12-141-0/+6
* treewide: s/comparitor/comparator/Ilia Mirkin2016-12-121-1/+1
* i965: enable INTEL_conservative_rasterization on Gen9+Lionel Landwerlin2016-12-071-0/+1
* i965/fs: Refactor handling of constant tg4 offsetsJason Ekstrand2016-11-291-1/+1
* i965: Use 3DSTATE_CLIP's User Clip Distance Enable bitmask on Gen8+.Kenneth Graunke2016-11-231-0/+1
* i965/ir: Update several stale comments.Francisco Jerez2016-09-141-1/+1
* i965/fs: Define logical framebuffer read opcode and lower it to physical reads.Francisco Jerez2016-08-251-0/+1
* i965/fs: Define framebuffer read virtual opcode.Francisco Jerez2016-08-251-0/+3
* i965/eu: Add codegen support for the Gen9+ render target read message.Francisco Jerez2016-08-251-0/+4
* i965: Fix undefined signed overflow in INTEL_MASK for bitfields of 31 bits.Francisco Jerez2016-08-251-1/+1
* i965: Roll intel_reg.h into brw_defines.hJason Ekstrand2016-08-191-0/+273
* i965: Delete the FS_OPCODE_INTERPOLATE_AT_CENTROID virtual opcode.Kenneth Graunke2016-07-201-1/+0
* i965: Rename brw_wm_barycentric_interp_mode to brw_barycentric_mode.Kenneth Graunke2016-07-151-12/+12
* i965: enable the emission of the DIM instructionSamuel Iglesias Gonsálvez2016-07-141-1/+1
* i965/docs: update Intel Linux Graphics URLsEric Engestrom2016-07-061-1/+1
* i965: Support new local ID push constant & cross-thread constantsJordan Justen2016-06-011-0/+3
* i965/fs: Implement opt_sampler_eot() in terms of logical sends.Francisco Jerez2016-05-291-0/+1
* i965/ir: Make BROADCAST emit an unmasked single-channel move.Francisco Jerez2016-05-271-0/+6
* i965/fs: Remove FS_OPCODE_PACK_STENCIL_REF virtual instruction.Francisco Jerez2016-05-271-1/+0
* i965/fs: Remove extract virtual opcodes.Francisco Jerez2016-05-271-12/+0
* i965/fs: Handle SAMPLEINFO consistently like other texturing instructions.Francisco Jerez2016-05-271-0/+1
* i965/fs: Rename Gen4 physical varying pull constant load opcode.Francisco Jerez2016-05-271-1/+1
* i965/fs: Hide varying pull constant load message setup behind logical opcode.Francisco Jerez2016-05-271-0/+1
* i965, anv: Use NIR FragCoord re-center and y-transform passes.Kenneth Graunke2016-05-201-1/+0
* i965: Add infrastucture for sample lod-zero operations.Matt Turner2016-05-191-0/+5
* i965/blorp: Delete the old blorp shader emit codeJason Ekstrand2016-05-141-1/+0
* i965/gen9: Prepare surface state setup for lossless compressionTopi Pohjolainen2016-05-121-0/+1
* i965/fs: add PACK opcodeConnor Abbott2016-05-101-0/+9
* i965/gen7: Use predicated rendering for indirect computeJordan Justen2016-02-171-0/+1
* i965: Add resolve option for lossless compressionTopi Pohjolainen2016-02-161-0/+1
* i965/fs: Plumb separate surfaces and samplers through from NIRJason Ekstrand2016-02-091-1/+3
* i965/fs: Add an enum for keeping track of texture instruciton sourcesJason Ekstrand2016-02-091-13/+27
* i965/fs: Implement support for extract_word.Matt Turner2016-02-011-0/+12
* i965: Don't set interleave or complete on TCS EOT message.Kenneth Graunke2015-12-281-0/+1
* i965: Relase input URB Handles on Gen7/7.5 when TCS threads finish.Kenneth Graunke2015-12-281-0/+2
* i965: Port tessellation evaluation shaders to vec4 mode.Kenneth Graunke2015-12-281-0/+4
* i965: Add tessellation control shaders.Kenneth Graunke2015-12-221-0/+8
* i965: Enable shared local memory for CS shared variablesJordan Justen2015-12-091-0/+2
* i965: Define and use REG_MASK macro to make masked MMIO writes slightly more ...Francisco Jerez2015-12-091-0/+6
* i965: Add defines for gather push constantsAbdiel Janulgue2015-12-071-0/+19
* i965: Add symbolic defines for some magic dataport surface indices.Francisco Jerez2015-11-261-0/+13
* i965: Add more MAX_*_URB_ENTRY_SIZE_BYTES #defines.Kenneth Graunke2015-11-171-0/+6
* i965: Introduce a MOV_INDIRECT opcode.Kenneth Graunke2015-11-141-0/+10
* i965: Add a SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT opcode.Kenneth Graunke2015-11-131-5/+2
* i965: Combine register file field.Matt Turner2015-11-131-0/+11
* i965: Add and use enum brw_reg_file.Matt Turner2015-11-131-4/+6
* i965: Fill out instruction list.Matt Turner2015-11-121-7/+31
* i965: Map GL_PATCHES to 3DPRIM_PATCHLIST_n.Kenneth Graunke2015-11-111-0/+2
* i965/fs/skl+: Use ld2dms_w instead of ld2dmsNeil Roberts2015-11-051-0/+3
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