summaryrefslogtreecommitdiffstats
path: root/src/mesa/drivers/dri/i965/brw_defines.h
Commit message (Expand)AuthorAgeFilesLines
* i965/chv|skl: Apply sampler bypass w/aBen Widawsky2015-08-311-0/+1
* i965/surface_formats: add support for 2D ASTC surface formatsNanley Chery2015-08-261-0/+32
* i965/gen7-8: Set up early depth/stencil control appropriately for image load/...Francisco Jerez2015-08-111-0/+3
* i965/gen7-8: Poke the 3DSTATE UAV access enable bits.Francisco Jerez2015-08-111-0/+4
* i965: Define virtual instruction to calculate the high 32 bits of a multiply.Francisco Jerez2015-08-061-0/+5
* i965/fs: Define logical typed and untyped surface opcodes.Francisco Jerez2015-07-291-0/+20
* i965/fs: Define logical texture sampling opcodes.Francisco Jerez2015-07-291-0/+31
* i965/fs: Remove the FS_OPCODE_SET_OMASK pseudo-opcode.Francisco Jerez2015-07-291-1/+0
* i965/fs: Define logical framebuffer write opcode.Francisco Jerez2015-07-291-0/+15
* i965: Define HW-binding table and resource streamer control opcodesAbdiel Janulgue2015-07-181-0/+30
* i965/gen9: Use custom MOCS entries set up by the kernel.Francisco Jerez2015-07-161-5/+6
* i965/cs: Initialize GPGPU Thread CountJordan Justen2015-07-141-0/+5
* i965/skl: Set the pulls bary bit in 3DSTATE_PS_EXTRANeil Roberts2015-07-061-0/+1
* i965/gen9: Don't use encrypted MOCSBen Widawsky2015-06-231-2/+2
* i965/gen9: Disable Mip Tail for YF/YS tiled surfacesAnuj Phogat2015-06-161-0/+3
* i965/gen9: Set tiled resource mode in surface stateAnuj Phogat2015-06-161-0/+6
* i965/fs: Implement support for ir_barrierJordan Justen2015-06-121-0/+5
* i965: Add GATEWAY_SFID definitionsJordan Justen2015-06-121-0/+8
* i965: Create a shader_dispatch_mode enum to replace VS/GS fields.Kenneth Graunke2015-06-011-3/+2
* i965: Add Gen9 surface state decodingBen Widawsky2015-05-181-0/+2
* i965: Add gen8 surface state debug infoBen Widawsky2015-05-181-1/+3
* i965: Add gen7+ sampler state to batch debugBen Widawsky2015-05-181-0/+1
* i965: Use predicate enable bit for conditional rendering w/o stallingNeil Roberts2015-05-121-0/+1
* i965/gen6: setup limits for ARB_viewport_arrayChris Forbes2015-05-061-1/+1
* i965: Introduce the FIND_LIVE_CHANNEL pseudo-opcode.Francisco Jerez2015-05-041-0/+8
* i965: Introduce the BROADCAST pseudo-opcode.Francisco Jerez2015-05-041-0/+6
* i965: Add memory fence opcode.Francisco Jerez2015-05-041-0/+2
* i965: Add typed surface access opcodes.Francisco Jerez2015-05-041-0/+4
* i965: Add untyped surface write opcode.Francisco Jerez2015-05-041-0/+1
* i965/cs: Emit MEDIA_STATE_FLUSH after WALKERJordan Justen2015-05-021-0/+1
* i965/cs: Implement brw_emit_gpgpu_walkerJordan Justen2015-05-021-0/+13
* i965/cs: Upload brw_cs_stateJordan Justen2015-05-021-0/+20
* i965/cs: Add CS_OPCODE_CS_TERMINATEJordan Justen2015-05-021-0/+5
* i965/ps: Use SET_FIELD() for sampler countTopi Pohjolainen2015-04-301-0/+1
* i965/fs: Combine pixel center calculation into one inst.Matt Turner2015-04-211-0/+2
* i965/fs: Emit ADDs for gl_FragCoord, not virtual opcodes.Matt Turner2015-04-211-2/+0
* i965/skl: Add the header for constant loads outside of the generatorNeil Roberts2015-04-161-0/+1
* i965: Add missing defines for render cache messages.Francisco Jerez2015-03-021-1/+7
* i965/vec4: Add and use byte-MOV instruction for unpack 4x8.Matt Turner2015-02-191-0/+1
* i965: Fix integer border color on Haswell.Kenneth Graunke2015-02-091-0/+1
* i965/skl: Always use a header for SIMD4x2 sampler messagesKristian Høgsberg2015-01-081-0/+5
* i965: Add new SIMD8 VS prog data flagKristian Høgsberg2014-12-101-0/+2
* i965: Add SIMD8 URB write low-level IR instructionKristian Høgsberg2014-12-101-0/+3
* i965/vec4: Allow CSE on uniform-vec4 expansion MOVs.Matt Turner2014-12-051-0/+1
* i965: Move PSCDEPTH calculations from draw time to compile time.Kenneth Graunke2014-12-041-8/+9
* i965/fs: Pass key->render_to_fbo via src1 of FS_OPCODE_DDY_*.Kenneth Graunke2014-11-271-0/+4
* i965/fs: Handle derivative quality decisions in the front-end.Kenneth Graunke2014-11-271-8/+4
* i965/vec4: Add VEC4_OPCODE_PACK_4_BYTES.Matt Turner2014-11-251-0/+2
* i965/disasm: Properly decode branch_ctrl (gen8+)Ben Widawsky2014-11-201-0/+1
* i965: Set Line Width correctly on Cherryview and Skylake.Kenneth Graunke2014-11-081-0/+1
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-28 08:45:52 +0000