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path: root/src/mesa/drivers/dri/i965/brw_context.h
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* i965/gen6+: Merge VS/GS and WM push constant buffer upload paths.Eric Anholt2014-07-021-5/+5
* i965: Move dispatch_grf_start_reg and first_curbe_grf into stage_prog_data.Eric Anholt2014-07-021-8/+7
* i965: Remove a dead define.Eric Anholt2014-07-021-2/+0
* i965: Reuse libdrm's header for AUB definitions.Eric Anholt2014-07-021-67/+3
* i965: Fix stale comments about the state cache.Eric Anholt2014-07-021-1/+8
* i965: Drop the memcmp for finding duplicated CURBE uploads.Eric Anholt2014-07-021-14/+0
* i965: Reuse intel_upload.c for gen4/5 constant buffers.Eric Anholt2014-07-021-2/+4
* i965: Add is_cherryview flag to brw_context.Matt Turner2014-06-261-0/+1
* i965: Replace 'struct brw_instruction' with 'brw_inst'.Matt Turner2014-06-261-2/+2
* i965: Pass brw rather than gen to brw_disassemble_inst().Matt Turner2014-06-261-2/+2
* i965: Save meta stencil blit programs in the context.Kenneth Graunke2014-06-211-0/+3
* i965: Rename brw_disasm/gen8_disassemble to brw/gen8_disassemble_inst.Kenneth Graunke2014-05-181-1/+2
* i965/disasm: Disassemble the compaction control bit.Matt Turner2014-05-151-1/+1
* i965/meta: Stencil blit for miptree updownsamplingTopi Pohjolainen2014-05-151-0/+4
* i965/meta: Stencil blitsTopi Pohjolainen2014-05-151-0/+6
* i965: Extend brw_get_rb_for_first_slice() for specified level/layerTopi Pohjolainen2014-05-151-0/+4
* i965/gen7+: Move sampler state packets to the stage sampler state table update.Eric Anholt2014-05-021-0/+1
* i965: Simplify sampler setup by passing the stage state.Eric Anholt2014-05-021-3/+1
* i965: Actually emit PIPELINE_SELECT and 3DSTATE_VF_STATISTICS.Kenneth Graunke2014-05-011-5/+0
* i965: Track the number of samples in the drawbuffer.Eric Anholt2014-04-301-0/+8
* i965: Stop setting up a 1:1 "attrib" member in our vertex inputs.Eric Anholt2014-04-111-2/+0
* i965/gen7: Skip repeated NULL depth/stencil state emits.Eric Anholt2014-04-111-0/+3
* mesa: Move is_power_of_two() function from brw_context.h to macros.h.Kenneth Graunke2014-04-081-6/+0
* i965: Use intel_upload_space() for pull constant uploads.Eric Anholt2014-03-261-3/+0
* i965: Massively simplify the intel_upload implementation.Eric Anholt2014-03-261-4/+1
* i965/gen8: Change the winsys MSAA blits from blorp to meta.Eric Anholt2014-03-241-0/+6
* i965: Drop some more dead code from the old CACHED_BATCH feature.Eric Anholt2014-03-181-9/+0
* i965: Allocate register sets at screen creation, not context creation.Kenneth Graunke2014-03-181-44/+2
* i965: Fix register types in dump_instructions(), again.Kenneth Graunke2014-03-141-1/+0
* i965: Drop broken front_buffer_reading/drawing optimization.Eric Anholt2014-03-111-17/+0
* i965: Fix render-to-texture in non-FinishRenderTexture cases.Eric Anholt2014-03-061-0/+7
* glsl/i965: move lower_offset_array up to GLSL compiler level.Dave Airlie2014-02-251-1/+0
* i965: support instanced GS on gen7Jordan Justen2014-02-201-0/+2
* i965: Move up duplicated fields from stage-specific prog_data to brw_stage_pr...Francisco Jerez2014-02-191-19/+13
* i965: Implement HiZ resolves on Broadwell.Kenneth Graunke2014-02-191-0/+4
* i965: Pull format conversion logic out of brw_depthbuffer_format.Kenneth Graunke2014-02-191-0/+1
* i965: Implement a brw_load_register_mem helper function.Kenneth Graunke2014-02-071-0/+7
* i965/cs: Create the brw_compute_program struct, and the code to initialize it.Paul Berry2014-02-051-0/+8
* i965: Create drm_intel_bo_map wrappers with performance warnings.Kenneth Graunke2014-02-031-0/+6
* i965: Update multisampling state for Broadwell.Kenneth Graunke2014-01-311-0/+4
* i965: Update 3DSTATE_{DEPTH,STENCIL,...}_BUFFER and such for Broadwell.Kenneth Graunke2014-01-311-0/+9
* i965: Update SOL state for Broadwell.Kenneth Graunke2014-01-311-0/+3
* i965: Rework vertex uploads for Broadwell.Kenneth Graunke2014-01-311-0/+1
* mesa: change gl_format to mesa_formatMark Mueller2014-01-271-1/+1
* i965: Support 32 texture image units on Haswell+.Kenneth Graunke2014-01-221-1/+1
* i965: Add GS support to INTEL_DEBUG=shader_time.Paul Berry2014-01-211-0/+3
* i965: Re-combine the Gen4-5 and Gen6+ write_depth_count functions.Kenneth Graunke2014-01-201-0/+1
* i965: Use the new drm_intel_bo offset64 field.Kenneth Graunke2014-01-201-1/+1
* i965: Stop doing our optimization on a copy of the GLSL IR.Eric Anholt2014-01-171-3/+0
* s/Tungsten Graphics/VMware/José Fonseca2014-01-171-2/+2
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