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path: root/src/mesa/drivers/dri/i965/brw_context.h
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* i965: Add device limits for tess threads & URB entriesChris Forbes2015-02-171-0/+4
* i965: Do Sandybridge workaround flushes before each primitive.Kenneth Graunke2015-02-171-1/+0
* i965: Generalize the update_null_renderbuffer_surface vtbl hook to non-render...Francisco Jerez2015-02-101-3/+6
* i965: Allocate binding table space for shader images.Francisco Jerez2015-02-101-0/+5
* DD: Refactor BlitFramebuffer.Laura Ekstrand2015-02-021-0/+4
* i965: Enable L3 caching of buffer surfaces.Francisco Jerez2015-01-311-1/+0
* i965: Store the atoms directly in the contextIan Romanick2015-01-141-1/+1
* i965: Micro-optimize brw_get_index_typeIan Romanick2015-01-141-1/+21
* i965: Implement WaCsStallAtEveryFourthPipecontrol on IVB/BYT.Kenneth Graunke2015-01-041-0/+2
* i965: Fix start/base_vertex_location for >1 prims but !BRW_NEW_VERTICES.Kenneth Graunke2014-12-311-5/+2
* i965/query: Cache whether the batch references the query BO.Kenneth Graunke2014-12-161-0/+3
* i965: Generate vs code using scalar backend for BDW+Kristian Høgsberg2014-12-101-0/+1
* i965: Rename brw_vec4_prog_data/key to brw_bue_prog_data/keyKristian Høgsberg2014-12-101-8/+8
* i965: Add new SIMD8 VS prog data flagKristian Høgsberg2014-12-101-1/+4
* i965: Compute VS attribute WA bits earlier and check if they changed.Kenneth Graunke2014-12-041-0/+10
* i965: Store floating point mode choice in brw_stage_prog_data.Kenneth Graunke2014-12-041-0/+2
* i965: Move PSCDEPTH calculations from draw time to compile time.Kenneth Graunke2014-12-041-0/+2
* i965: Delete brw_state_flags::cache and related code.Kenneth Graunke2014-12-021-11/+1
* i965: Move BRW_NEW_*_PROG_DATA flags to .brw (not .cache).Kenneth Graunke2014-12-021-23/+46
* i965: Rename CACHE_NEW_*_PROG to BRW_NEW_*_PROG_DATA.Kenneth Graunke2014-12-021-8/+8
* i965: Remove "disable_derivative_optimization" driconf option.Kenneth Graunke2014-12-021-1/+0
* i965: Add _CACHE_ in brw_cache_id enum names.Kenneth Graunke2014-11-291-14/+14
* i965: Move CACHE_NEW_SAMPLER to BRW_NEW_SAMPLER_STATE_TABLE.Kenneth Graunke2014-11-291-2/+2
* i965: Move CACHE_NEW_*_VP flags to BRW_NEW_*_VP.Kenneth Graunke2014-11-291-6/+6
* i965: Combine CACHE_NEW_*_UNIT into BRW_NEW_GEN4_UNIT_STATE.Kenneth Graunke2014-11-291-12/+2
* i965: Implement the PMA stall fix.Kenneth Graunke2014-11-041-0/+3
* i965: Skip recalculating URB allocations if the entry size didn't change.Eric Anholt2014-10-241-2/+3
* i965: Add new dirty flag for new TexBOs.Chris Forbes2014-10-161-0/+2
* i965: Initialize the SampleMap{2,4,8}x variablesAnuj Phogat2014-10-011-0/+2
* i965: Use "1ull" instead of "1" in BRW_NEW_* defines.Kenneth Graunke2014-10-011-32/+32
* i965: Delete CACHE_NEW_BLORP_CONST_COLOR_PROG.Kenneth Graunke2014-10-011-2/+0
* i965/gen6/gs: Fix binding table clash between TF surfaces and textures.Iago Toral Quiroga2014-09-191-2/+6
* i965/gen6/gs: implement transform feedback support in gen6_gs_visitorSamuel Iglesias Gonsalvez2014-09-191-42/+71
* i965/gs: Use single dispatch mode as fallback to dual object mode when possible.Iago Toral Quiroga2014-09-191-3/+5
* i965: Separate gl_InstanceID and gl_VertexID uploading.Kenneth Graunke2014-09-121-0/+1
* i965: Make gl_BaseVertex available in a buffer object.Kenneth Graunke2014-09-101-0/+7
* i965: Calculate start/base_vertex_location after preparing vertices.Kenneth Graunke2014-09-101-0/+8
* i965: Add uses_kill to brw_wm_prog_dataJordan Justen2014-09-051-0/+1
* Revert 5 i965 patches: 8e27a4d2, 373143ed, c5bdf9be, 6f56e142, 88e3d404Jordan Justen2014-09-041-65/+3
* i965: Move curb_read_length/total_scratch to brw_stage_prog_data.Kenneth Graunke2014-09-031-4/+3
* mesa: Convert NewDriverState to 64-bitsJordan Justen2014-09-011-1/+13
* i965: Modify state upload to allow 2 different sets of state atoms.Paul Berry2014-09-011-2/+2
* i965: Modify dirty bit handling to support 2 pipelines.Paul Berry2014-09-011-5/+31
* i965: Create a macro for checking a dirty bit.Paul Berry2014-09-011-0/+6
* i965: Create a macro for setting all dirty bits.Paul Berry2014-09-011-0/+11
* i965: Create a macro for setting a dirty bit.Paul Berry2014-09-011-0/+7
* i965: Split gen6 depth hiz state out from brwJordan Justen2014-08-151-0/+10
* i965: Implement fast color clears using meta operationsKristian Høgsberg2014-08-151-0/+15
* i965: Add optimization pass to let us use the replicate data messageKristian Høgsberg2014-08-151-0/+1
* i965: Provide a context flag to let us enable fast clearKristian Høgsberg2014-08-151-0/+1
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