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path: root/src/mesa/drivers/dri/i965/brw_context.c
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* util: move brw_env_var_as_boolean() to utilRob Clark2015-11-241-2/+3
* i965: Set MaxCombinedUniformBlocks properly.Kenneth Graunke2015-11-161-0/+1
* i965: Clean up context constant initialization code.Kenneth Graunke2015-11-161-80/+54
* i965: Convert scalar_* flags to a scalar_stage array.Kenneth Graunke2015-11-161-1/+1
* i965/skl+: Enable support for 16x multisamplingNeil Roberts2015-11-051-0/+6
* i965: Move the entire compiler API into a single fileJason Ekstrand2015-10-191-1/+1
* mesa/i965: Refactor brw_is_front_buffer_{drawing,reading} to common codeIan Romanick2015-10-061-7/+8
* i965: Define BRW_MAX_SSBOIago Toral Quiroga2015-10-051-7/+7
* i965: Define BRW_MAX_UBOIago Toral Quiroga2015-10-051-2/+2
* i965: Remove early release of DRI2 miptreeChris Wilson2015-09-301-1/+0
* i965: Set MaxShaderStorageBuffers for compute shadersIago Toral Quiroga2015-09-251-0/+3
* i965: set ARB_shader_storage_buffer_object related constant valuesSamuel Iglesias Gonsalvez2015-09-251-0/+12
* i965: Use 64-byte offset alignment for shader storage buffersIago Toral Quiroga2015-09-251-0/+9
* i965: Advertise 65536 for GL_MAX_UNIFORM_BLOCK_SIZE.Kenneth Graunke2015-09-101-0/+9
* mesa: Rename MaxCombinedImageUnitsAndFragmentOutputs to MaxCombinedShaderOutp...Francisco Jerez2015-08-201-1/+1
* i965: Define implementation constants for ARB_shader_image_load_store.Francisco Jerez2015-08-111-0/+12
* i965: Enable hardware-generated binding tables on render path.Abdiel Janulgue2015-07-181-0/+4
* i965: Enable resource streamer for the batchbufferAbdiel Janulgue2015-07-181-0/+4
* i965: Move pipecontrol workaround bo to brw_pipe_controlChris Wilson2015-07-081-0/+7
* i965/bxt: Add basic Broxton infrastructureBen Widawsky2015-06-241-0/+1
* i965: Add compiler options to brw_compilerJason Ekstrand2015-06-231-43/+3
* i965: Move INTEL_DEBUG variable parsing to screen creation timeJason Ekstrand2015-06-231-1/+3
* i965: enable ARB_framebuffer_no_attachments for Gen7+Kevin Rogovin2015-06-171-0/+6
* Revert "i965: Advertise a line width of 40.0 on Cherryview and Skylake."Kenneth Graunke2015-06-111-5/+1
* i965: do not round line width when multisampling or antialiaing are enabledIago Toral Quiroga2015-06-111-0/+7
* i965: Set max texture buffer size to hardware limitChris Forbes2015-06-061-0/+1
* i965: Make NIR non-optional for scalar shadersJason Ekstrand2015-05-281-5/+2
* i965: Use NIR by default for vertex shaders on GEN8+Jason Ekstrand2015-05-181-1/+1
* i965: Use predicate enable bit for conditional rendering w/o stallingNeil Roberts2015-05-121-0/+4
* i965/gen6: setup limits for ARB_viewport_arrayChris Forbes2015-05-061-2/+2
* i965: Fix missing type in local variable declaration.Kenneth Graunke2015-05-051-1/+1
* i965: Implement DispatchCompute() back-endPaul Berry2015-05-021-0/+1
* i965/cs: Set invocation counts based on max_cs_threadsJordan Justen2015-05-021-0/+24
* i965/cs: Add max_cs_threadsJordan Justen2015-05-021-0/+1
* i965/fs: Support compute programs in fs_visitorJordan Justen2015-05-021-0/+2
* Fix a few typosZoë Blade2015-04-271-2/+2
* i965/device_info: Add a supports_simd16_3src flagJason Ekstrand2015-04-221-24/+0
* i965: replace __FUNCTION__ with __func__Marius Predut2015-04-141-2/+2
* i965: Remove useless null check.Matt Turner2015-04-111-4/+0
* nir: split out lower_sub from lower_negateRob Clark2015-04-111-0/+1
* i965: Use NIR by default for fragment shadersJason Ekstrand2015-04-101-1/+1
* i965: Don't set NirOptions for stages that will use the vec4 backend.cros-mesa-10.6-vanillachadv/cros-mesa-10.6-vanillachadv/cros-gerrit-262788-baseKenneth Graunke2015-04-101-9/+6
* i965: Check the INTEL_USE_NIR environment variable once at context creationJason Ekstrand2015-04-031-1/+9
* i965: Use the same nir options for all gensJason Ekstrand2015-04-011-10/+2
* i965/nir: Run the ffma peephole after the rest of the optimizationsJason Ekstrand2015-04-011-0/+5
* i965/nir: Use NIR lowering for ffma for gen < 6Jason Ekstrand2015-03-231-2/+10
* i965: define I915_PARAM_REVISIONDave Airlie2015-03-231-0/+5
* i965: Store the GPU revision number in brw_contextNeil Roberts2015-03-201-0/+19
* i965: Defer the throttle until we submit new commandsChris Wilson2015-03-181-34/+0
* i965: Throttle to the previous frameChris Wilson2015-03-181-7/+12
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