aboutsummaryrefslogtreecommitdiffstats
path: root/src/mesa/drivers/dri/i965/brw_clip_tri.c
Commit message (Expand)AuthorAgeFilesLines
* s/Tungsten Graphics/VMware/José Fonseca2014-01-171-2/+2
* i965: Drop trailing whitespace from the rest of the driver.Kenneth Graunke2013-12-051-40/+40
* i965: Combine 4 boolean args of brw_urb_WRITE into a flags bitfield.Paul Berry2013-08-231-3/+3
* i965: allow 8 user clip planes on CTG+Chris Forbes2013-08-161-2/+2
* i965/clip: remove spurious clipvertex paramChris Forbes2013-08-161-11/+4
* i965/clip: Use clip distances for all user clippingChris Forbes2013-08-161-5/+6
* i956/clip: push dp4 into load_clip_distanceChris Forbes2013-08-161-17/+22
* i965/clip: Track offset into the vertex for clipdistanceChris Forbes2013-08-161-0/+9
* i965 Gen4/5: clip: correctly handle flat varyingsChris Forbes2013-08-011-9/+9
* i965: Move intel_context::gen and gt fields to brw_context.Kenneth Graunke2013-07-091-2/+2
* i965: Replace intel_context:needs_ff_sync with intel->gen == 5.Kenneth Graunke2013-07-091-1/+1
* i965/clip: Add support for gl_ClipVertexChris Forbes2013-06-071-4/+44
* i965: Clarify nomenclature: vert_result -> varyingPaul Berry2013-03-231-3/+2
* Replace gl_vert_result enum with gl_varying_slot.Paul Berry2013-03-151-2/+2
* i965: Don't make consumers of brw_DO()/brw_WHILE() track loop start.Eric Anholt2011-12-211-9/+6
* i965: Clean up misleading defines for DWORD 2 of URB_WRITE header.Paul Berry2011-12-071-3/+8
* intel: Convert from GLboolean to 'bool' from stdbool.h.Kenneth Graunke2011-10-181-2/+2
* i965: clip: Convert computations to ..._to_offset() for clarity.Paul Berry2011-09-061-1/+1
* i965: clip: Modify brw_clip_tri_alloc_regs() to use the VUE map.Paul Berry2011-09-061-2/+5
* i965: clip: Move hpos_offest and ndc_offset into local functions.Paul Berry2011-09-061-6/+11
* i965: Move IF stack handling into the EU abstraction layer/brw_compile.Kenneth Graunke2011-05-171-37/+29
* i965: Reduce repeated calculation of the attribute-offset-in-VUE.Eric Anholt2010-07-191-4/+1
* mesa: rename src/mesa/shader/ to src/mesa/program/Brian Paul2010-06-101-1/+1
* i965: Set the correct provoking vertex for clipped first-mode trifans.Eric Anholt2010-05-141-3/+17
* intel: Clean up chipset name and gen num for IronlakeZhenyu Wang2010-04-211-1/+1
* Merge branch 'mesa_7_7_branch'Brian Paul2010-01-251-1/+0
|\
| * i965: Remove unnecessary headers.Vinson Lee2010-01-221-1/+0
* | intel: Replace IS_965 checks with context structure usage.Eric Anholt2009-12-221-1/+2
* | intel: Replace IS_IGDNG checks with intel->is_ironlake or needs_ff_sync.Eric Anholt2009-12-221-2/+3
|/
* i965: fix EXT_provoking_vertex supportRoland Scheidegger2009-11-111-3/+9
* i965: Postpone ff_sync message in CLIP kernel on IGDNGXiang, Haihao2009-07-301-2/+6
* i965: add support for new chipsetsXiang, Haihao2009-07-131-3/+10
* i965: fix for RHW workaroundXiang, Haihao2009-02-261-20/+56
* i965: Merge GM45 into the G4X chipset define.Eric Anholt2008-11-021-1/+1
* mesa: added "main/" prefix to includes, remove some -I paths from Makefile.te...Brian Paul2008-09-181-4/+4
* 965: Fix incorrect backface cullingKrzysztof Czurylo2008-08-211-10/+0
* i965: official name for GM45 chipsetXiang, Haihao2008-07-081-1/+1
* Revert "[i965] renable regative rhw test"Xiang, Haihao2008-04-171-7/+9
* [i965] renable regative rhw testZou Nan hai2008-01-311-9/+7
* i965: new integrated graphics chipset supportXiang, Haihao2008-01-291-8/+9
* i965: re-define the type of reg.loopcount.Xiang, Haihao2008-01-251-1/+1
* fix ppracer and bzflag issue with clip optimizationZou Nan hai2007-09-271-1/+0
* optimize 965 clipZou Nan hai2007-08-311-4/+103
* Add Intel i965G/Q DRI driver.Eric Anholt2006-08-091-0/+467
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-29 20:54:54 +0000