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* i965/state: Don't use brw->state.dirty.brwJordan Justen2015-03-311-2/+2
| | | | | | | | | | | | | | | Now, we only use ctx->NewDriverState. I used this bash & sed command in the i965 directory: for file in *.[ch] *.[ch]pp; do sed -i -e 's/state\.dirty\.brw/ctx.NewDriverState/g' $file done Followed by manual changes to brw_state_upload.c. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Delete brw_state_flags::cache and related code.Kenneth Graunke2014-12-021-3/+0
| | | | | | | | | It's been merged into brw_state_flags::brw for simplicity and efficiency. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Move CACHE_NEW_*_VP flags to BRW_NEW_*_VP.Kenneth Graunke2014-11-291-3/+4
| | | | | | | | | | | | We've been streaming these out for ages, so they basically have nothing to do with brw_state_cache.c. Saves 6 * sizeof(void *) bytes per context, as we won't have useless aux_compare/aux_free functions for them. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Fold the gen7_cc_viewport_state_pointer atom into brw_cc_vp.Kenneth Graunke2014-11-291-1/+8
| | | | | | | | | These always happen together; the extra atom just means another item to iterate through, flags to check, and a call through a function pointer. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Combine CACHE_NEW_*_UNIT into BRW_NEW_GEN4_UNIT_STATE.Kenneth Graunke2014-11-291-1/+1
| | | | | | | | | | | | | | | | | | | | | On Gen4-5, unit state is specified as indirect state, rather than commands. If any unit state changes, we upload it via brw_state_batch and arrange for 3DSTATE_PIPELINED_POINTERS to be re-emitted, which updates pointers to all unit state at once. Since there's only one command and state atom (brw_psp_urb_cs) that needs to know about this, there's no benefit to having six separate flags. We can combine CACHE_NEW_*_UNIT into a single flag. We also haven't cached these in a long time, so it doesn't make sense to use the "CACHE_NEW_" prefix. Instead, use the "BRW_NEW_" prefix. This also saves 12 * sizeof(void *) bytes of memory per context, as we remove useless aux_compare/aux_free functions for each CACHE bit. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Alphabetize brw_tracked_state flags and use a consistent style.Kenneth Graunke2014-11-291-3/+8
| | | | | | | | | | | | | | | | Most of the dirty flags were listed in some arbitrary order. Some used bonus parenthesis. Some put multiple flags on one line, others put one per line. Some used tabs instead of spaces...but only on some lines. This patch settles on one flag per line, in alphabetical order, using spaces instead of tabs, and sheds the unnecessary parentheses. Sorting was mostly done with vim's visual block feature and !sort, although I alphabetized short lists by hand; it was pretty manual. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* Revert 5 i965 patches: 8e27a4d2, 373143ed, c5bdf9be, 6f56e142, 88e3d404Jordan Justen2014-09-041-2/+2
| | | | | | | | | | | | | | | | | | | | | | Reverts * "i965: Modify state upload to allow 2 different sets of state atoms." 8e27a4d2b3e4e74e9a77446bce49607433d86be3 * "i965: Modify dirty bit handling to support 2 pipelines." 373143ed9187c4d4ce1e3c486b5dd0880d18ec8b * "i965: Create a macro for checking a dirty bit." c5bdf9be1eca190417998d548fd140c1eca37a54 Conflicts: src/mesa/drivers/dri/i965/brw_context.h * "i965: Create a macro for setting all dirty bits." 6f56e1424d923fd80c84090fbf4506c9eaaffea1 Conflicts: src/mesa/drivers/dri/i965/brw_blorp.cpp src/mesa/drivers/dri/i965/brw_state_cache.c src/mesa/drivers/dri/i965/brw_state_upload.c * "i965: Create a macro for setting a dirty bit." 88e3d404dad009d8cff5124cf8acee7daeaceb64 Signed-off-by: Jordan Justen <[email protected]>
* i965: Create a macro for setting a dirty bit.Paul Berry2014-09-011-2/+2
| | | | | | | This will make it easier to extend dirty bit handling to support compute shaders. Reviewed-by: Jordan Justen <[email protected]>
* i965: Fix stale comments about the state cache.Eric Anholt2014-07-021-1/+1
| | | | | | This changed in the state streaming work years ago. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Use the new drm_intel_bo offset64 field.Kenneth Graunke2014-01-201-1/+1
| | | | | | | | | | | | | | | | | | | libdrm 2.4.52 introduces a new 'uint64_t offset64' field, intended to replace the old 'unsigned long offset' field. To preserve ABI, libdrm continues to store the presumed offset in both locations. On Broadwell, a 64-bit kernel may place BOs at "high" (> 4G) addresses. However, with a 32-bit userspace, the 'unsigned long offset' field will only be 32-bit, which is not large enough to hold this value. We need to use a proper uint64_t (like the kernel does). Technically, a lot of this code doesn't affect Broadwell, so we could leave it using the old field. But it makes sense to just switch to the new, properly typed field. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965: Set all the supported viewports for GEN7Ian Romanick2014-01-201-8/+13
| | | | | | | Currently MaxViewports is still 1, so this won't affect any change. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: Convert gl_context::Viewport to gl_context::ViewportArrayCourtney Goeltzenleuchter2014-01-201-2/+2
| | | | | | | | | | | Only element 0 of the array is used anywhere at this time, so there should be no changes. v4: Split out from a single megapatch. Suggested by Ken. Signed-off-by: Courtney Goeltzenleuchter <[email protected]> Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Remove CACHED_BATCH support altogether.Kenneth Graunke2014-01-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Using an unoptimized variant of glamor spending 50% of its CPU time in brw_draw_prims() (and hitting the cache *very* frequently): N Min Max Median Avg Stddev x 200 29200 40500 34900 34750 958.43256 + 200 31000 40300 34700 34622 916.35941 No difference proven at 95.0% confidence Similarly, no difference on GLB2.7: N Min Max Median Avg Stddev x 63 64.1 71.36 70.69 70.113175 1.6782026 + 63 63.6 71.18 70.75 70.223651 1.6044186 No difference proven at 95.0% confidence v2: Rebase on master (by anholt) v3: Add a missing BEGIN_BATCH(3) to aa_line_parameters -- CACHED_BATCH didn't have the asserts about batchbuffer usage that ADVANCE_BATCH does, so we started assertion failing. Signed-off-by: Kenneth Graunke <[email protected]> Signed-off-by: Eric Anholt <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* s/Tungsten Graphics/VMware/José Fonseca2014-01-171-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tungsten Graphics Inc. was acquired by VMware Inc. in 2008. Leaving the old copyright name is creating unnecessary confusion, hence this change. This was the sed script I used: $ cat tg2vmw.sed # Run as: # # git reset --hard HEAD && find include scons src -type f -not -name 'sed*' -print0 | xargs -0 sed -i -f tg2vmw.sed # # Rename copyrights s/Tungsten Gra\(ph\|hp\)ics,\? [iI]nc\.\?\(, Cedar Park\)\?\(, Austin\)\?\(, \(Texas\|TX\)\)\?\.\?/VMware, Inc./g /Copyright/s/Tungsten Graphics\(,\? [iI]nc\.\)\?\(, Cedar Park\)\?\(, Austin\)\?\(, \(Texas\|TX\)\)\?\.\?/VMware, Inc./ s/TUNGSTEN GRAPHICS/VMWARE/g # Rename emails s/[email protected]/[email protected]/ s/[email protected]/[email protected]/g s/jrfonseca-at-tungstengraphics-dot-com/jfonseca-at-vmware-dot-com/ s/jrfonseca\[email protected]/[email protected]/g s/keithw\[email protected]/[email protected]/g s/[email protected]/[email protected]/g s/thomas-at-tungstengraphics-dot-com/thellstom-at-vmware-dot-com/ s/[email protected]/[email protected]/ # Remove dead links s@Tungsten Graphics (http://www.tungstengraphics.com)@Tungsten Graphics@g # C string src/gallium/state_trackers/vega/api_misc.c s/"Tungsten Graphics, Inc"/"VMware, Inc"/ Reviewed-by: Brian Paul <[email protected]>
* i965: Drop trailing whitespace from the rest of the driver.Kenneth Graunke2013-12-051-4/+4
| | | | | | | Performed via: $ for file in *; do sed -i 's/ *//g'; done Signed-off-by: Kenneth Graunke <[email protected]>
* i965: Gen4-5: Don't enable hardware alpha test with MRTChris Forbes2013-11-061-1/+2
| | | | | | | | We have to do this in the shader instead, since these gens lack an independent RT0 alpha value in their render target write messages. Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Delete intel_context entirely.Kenneth Graunke2013-07-091-4/+3
| | | | | | | | | | This makes brw_context inherit directly from gl_context; that was the only thing left in intel_context. Signed-off-by: Kenneth Graunke <[email protected]> Acked-by: Chris Forbes <[email protected]> Acked-by: Paul Berry <[email protected]> Acked-by: Anuj Phogat <[email protected]>
* i965: Move intel_context::stats_wm to brw_context.Kenneth Graunke2013-07-091-2/+1
| | | | | | | Signed-off-by: Kenneth Graunke <[email protected]> Acked-by: Chris Forbes <[email protected]> Acked-by: Paul Berry <[email protected]> Acked-by: Anuj Phogat <[email protected]>
* i965: Move intel_context::batch to brw_context.Kenneth Graunke2013-07-091-3/+3
| | | | | | | Signed-off-by: Kenneth Graunke <[email protected]> Acked-by: Chris Forbes <[email protected]> Acked-by: Paul Berry <[email protected]> Acked-by: Anuj Phogat <[email protected]>
* intel: Stop doing special _NEW_STENCIL state flagging on drawbuffers.Eric Anholt2013-06-251-2/+2
| | | | | | | | 2/3 packets depending on Stencil._Enabled already checked for _NEW_BUFFERS, so just add _NEW_BUFFERS to the remaining one. Reviewed-by: Anuj Phogat <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel: Use accessor for stencil reference valuesChris Forbes2013-05-151-2/+3
| | | | | | | | | NOTE: This is a candidate for stable branches. Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Paul Berry <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* mesa: don't flag _NEW_DEPTH in Begin/EndQuery if driver implements the functionsMarek Olšák2013-04-241-1/+1
| | | | | | | | | | | We don't want to set the flag for Gallium. I think only swrast needs the flag to be set for occlusion queries. v2: fix stats_wm updates in i965 Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Avoid blending with destination alpha when RB format has no alpha bitsCarl Worth2013-01-141-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | The hardware does not support a render target without an alpha channel. So when the user creates a render buffer with no alpha channel, there actually is storage available for alpha internally. It requires special care to avoid these unwanted alpha bits from causing any problems. Specifically, when blending, and when the blend factors would read the destination alpha values, this commit coerces the blend factors to instead be either 0 or 1 as appropriate. A similar fix was made for pre-gen6 hardware in commit eadd9b8e and this commit shares the fixup function written by Ian then. This commit the following es3conform test: rgb8_rgba8_rgb As well as the following piglit (sub) tests: EXT_framebuffer_object/fbo-blending-formats/3 EXT_framebuffer_object/fbo-blending-formats/GL_RGB EXT_framebuffer_object/fbo-blending-formats/GL_RGB8 Reviewed-by: Ian Romanick <[email protected]>
* i965: Correct _NEW_TRANSOFORM typos.Kenneth Graunke2012-01-071-1/+1
| | | | | | Using the proper spelling, _NEW_TRANSFORM, makes searching work better. Signed-off-by: Kenneth Graunke <[email protected]>
* i965/gen4: Move CC VP to emit() time, since it's only needed by CC's emit().Eric Anholt2011-10-291-2/+2
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Acked-by: Paul Berry <[email protected]>
* mesa: Use ColorLogicOpEnabled instead of _LogicOpEnabledIan Romanick2011-09-191-1/+1
| | | | | | | | | | Since GL_EXT_blend_logic_op is removed, _LogicOpEnabled and ColorLogicOpEnabled always have the same value. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* i965: Add a type argument to brw_state_batch().Eric Anholt2011-07-111-2/+4
| | | | | | | | | I want to make brw_state_dump.c handle more than just the last statechange, so I want to keep track of what's in the batch state. By using AUB file numbering for most of these packets, this may be reusable for aub dumping. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Move the CC VP to state streaming.Eric Anholt2011-04-291-18/+21
| | | | | | | | This is in a way a revert of f5bb775fd1f333d8e579d07a5cac1ded2bd54a2f. The tiny win that had will be overwhelmed by the win of using the gen6 dynamic state base address. Reviewed-by: Kenneth Graunke <[email protected]>
* intel: Add support for ARB_color_buffer_float.Eric Anholt2011-04-201-4/+4
| | | | Reviewed-by: Brian Paul <[email protected]>
* i965: Remember to pack the constant blend color as floats into the batchChris Wilson2011-02-241-4/+4
| | | | | | | Fixes regression from aac120977d1ead319141d48d65c9bba626ec03b8. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=34597 Signed-off-by: Chris Wilson <[email protected]>
* i965: Move repeat-instruction-suppression to batchbuffer coreChris Wilson2011-02-211-12/+10
| | | | | | | | Move the tracking of the last emitted instructions into the core batchbuffer routines and take advantage of the shadow batch copy to avoid extra memory allocations and copies. Signed-off-by: Chris Wilson <[email protected]>
* intel: use pwrite for batchChris Wilson2011-02-211-1/+1
| | | | | | | | | | | It's faster. Not only is the memcpy more efficiently performed in the kernel (making up for the system call overhead), but by not using mmap we remove the greater overhead of tracking the vma of every batch. And it means we can read back from the batch buffer without incurring the cost of a uncached read through the GTT. Signed-off-by: Chris Wilson <[email protected]>
* i965: drop state_bo references to batch_boChris Wilson2011-02-211-3/+3
| | | | | | | As we use state relocations and we know that all the state belongs to the same bo, we can drop the multiple references to the same bo. Signed-off-by: Chris Wilson <[email protected]>
* i965: write cc straight to batchChris Wilson2011-02-211-48/+46
| | | | | | | As we write directly into the batch in system memory, we do not need to write first to the stack (as was to avoid read back through the GTT) Signed-off-by: Chris Wilson <[email protected]>
* mesa: begin implementation of GL_ARB_draw_buffers_blendBrian Paul2011-01-151-6/+6
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* i965: Rename more #defines to 3DSTATE rather than CMD or CMD_3D.Kenneth Graunke2011-01-101-1/+1
| | | | Again, this makes it match the documentation.
* i965: Move gen4 blend constant color to the gen4 blending file.Eric Anholt2010-11-231-0/+25
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* intel: Annotate debug printout checks with unlikely().Eric Anholt2010-11-031-1/+1
| | | | | | | This provides the optimizer with hints about code hotness, which we're quite certain about for debug printouts (or, rather, while we developers often hit the checks for debug printouts, we don't care about performance while doing so).
* Drop GLcontext typedef and use struct gl_context insteadKristian Høgsberg2010-10-131-2/+2
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* i965: Also enable CC statistics when doing OQs.Eric Anholt2010-09-211-3/+4
| | | | This is required by the spec, so respect that.
* i965: Stream out CC unit state.Eric Anholt2010-06-121-153/+63
| | | | | | | | before: [ # ] backend test min(s) median(s) stddev. count [ 0] gl firefox-talos-gfx 31.791 32.287 1.11% 6/6 after: [ 0] gl firefox-talos-gfx 31.198 31.675 0.96% 6/6
* i965: GC the last two arguments to brw_cache_data.Eric Anholt2010-06-111-2/+1
| | | | | Now that the binding table is streamed indirect state, they were always NULL/0.
* i965: Set the CC VP state immediately on state change.Eric Anholt2010-06-111-10/+2
| | | | | | | | The cache lookup of these two little floats was .12% of total CPU time on firefox-talos-gfx because we did it any time commonly-changed state changed. On the other hand, updating the CC VP bo immediately whenver CC VP state changes is a .07% overhead due to putting a driver hoook in glEnable().
* intel: Convert remaining dri_bo_emit_reloc to drm_intel_bo_emit_reloc.Eric Anholt2010-06-081-6/+3
| | | | | The new API makes so much more sense, I'd like to forget how the old one worked.
* intel: Change dri_bo_* to drm_intel_bo* to consistently use new API.Eric Anholt2010-06-081-4/+4
| | | | | The slightly less mechanical change of converting the emit_reloc calls will follow.
* Merge branch 'mesa_7_7_branch'Brian Paul2010-01-251-2/+0
|\ | | | | | | | | | | | | | | | | | | | | Conflicts: src/mesa/drivers/dri/intel/intel_screen.c src/mesa/drivers/dri/intel/intel_swapbuffers.c src/mesa/drivers/dri/r300/r300_emit.c src/mesa/drivers/dri/r300/r300_ioctl.c src/mesa/drivers/dri/r300/r300_tex.c src/mesa/drivers/dri/r300/r300_texstate.c
| * i965: Remove unnecessary headers.Vinson Lee2010-01-221-2/+0
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* | i965: Allow for variable-sized auxdata in the state cache.Eric Anholt2010-01-191-2/+1
|/ | | | | | Everything has been constant-sized until now, but constant buffer handling changes will make us want some additional variable sized array.
* i965: Use current draw buffer instead of drawable visual to get alpha bitsIan Romanick2009-12-141-2/+2
| | | | | | | | Use the currently bound draw buffer instead of the visual from the drawable used to create the context. This cause problems generating mipmaps for an RGBA texture in an RGB context. This fixes the failure in piglit's glsl-lod-bias test reported in bug #25614.
* i965: Fix handling of drawing to MESA_FORMAT_XRGB8888Ian Romanick2009-12-101-0/+34
| | | | | | | It turns out that 965 and friends cannot actually render to an xRGB surfaces. Instead, the surface has to be RGBA with writes to alpha disabled and the blend function modified to always use 1.0 for destination alpha.
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