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* i965: remove unused hal hooksDave Airlie2008-02-141-1/+0
| | | | These don't appear to have ever been used.
* [965] Enable EXT_framebuffer_object.Eric Anholt2007-12-201-0/+3
| | | | | To do so, merge the remainnig necessary code from the buffers, blit, span, and screen code to shared, and replace it with those.
* [965] Move to using shared texture management code.Eric Anholt2007-12-161-0/+2
| | | | | | This removes the delayed texture upload optimization from 965, in exchange for bringing us closer to PBO support. It also disables SGIS_generate_mipmap, which didn't seem to be working before anyway, according to the lodbias demo.
* [965] Replace the state cache suballocator with direct dri_bufmgr use.Eric Anholt2007-12-141-1/+0
| | | | | | | | | | | | | | | | | | | | | | | The user-space suballocator that was used avoided relocation computations by using the general and surface state base registers and allocating those types of buffers out of pools built on top of single buffer objects. It also avoided calls into the buffer manager for these small state allocations, since only one buffer object was being used. However, the buffer allocation cost appears to be low, and with relocation caching, computing relocations for buffers is essentially free. Additionally, implementing the suballocator required a don't-fence-subdata flag to disable waiting on buffer maps so that writing new data didn't block on rendering using old data, and careful handling when mapping to update old data (which we need to do for unavoidable relocations with FBOs). More importantly, when the suballocator filled, it had no replacement algorithm and just threw out all of the contents and forced them to be recomputed, which is a significant cost. This is the first step, which just changes the buffer type, but doesn't yet improve the hash table to not result in full recompute on overflow. Because the buffers are all allocated out of the general buffer allocator, we can no longer use the general/surface state bases to avoid relocations, and they are set to 0 instead.
* [965] Convert the driver to dri_bufmgr interface and enable TTM.Eric Anholt2007-12-071-1/+3
| | | | | | | | | | | | | This is currently believed to work but be a significant performance loss. Performance recovery should be soon to follow. The dri_bo_fake_disable_backing_store() call was added to allow backing store disable like bufmgr_fake.c did, which is a significant performance win (though it's missing the no-fence-subdata part). This commit is a squash merge of the 965-ttm branch, which had some history I wanted to avoid pulling due to noisiness and brokenness at many points for git-bisecting.
* [965] Replace 965 texture format code with common code.Eric Anholt2007-11-201-0/+1
| | | | | The only functional difference should be that 965 now gets the optimization where textures default to 16bpp when the screen is 16bpp.
* Merge branch 'origin'Eric Anholt2007-10-291-0/+1
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| * Merge branch '965-glsl'Zou Nan hai2007-10-261-0/+1
| |\ | | | | | | | | | | | | | | | | | | Conflicts: src/mesa/drivers/dri/i965/brw_sf.h src/mesa/drivers/dri/i965/intel_context.c
| | * support branch and loop in pixel shaderZou Nan hai2007-06-211-0/+1
| | | | | | | | | | | | most of the sample working with some small modification
* | | Replace symlink generation from i915 with files in intel/ and symlinks there.Eric Anholt2007-10-161-15/+2
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* | [965] Add batchbuffer dumping under INTEL_DEBUG=bat, like 915.Eric Anholt2007-09-271-0/+2
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* | Revert "WIP 965 conversion to dri_bufmgr."Eric Anholt2007-09-271-1/+1
| | | | | | | | | | | | | | This reverts commit b2f1aa2389473ed09170713301b042661d70a48e. Somehow I ended up with my branch's save-this-while-I-work-on-master commit actually on master.
* | WIP 965 conversion to dri_bufmgr.Eric Anholt2007-09-271-1/+1
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* | [965] Remove AUB file support.Eric Anholt2007-09-271-2/+0
| | | | | | | | | | This code existed to dump logs of hardware access to be replayed in simulation. Since we have real hardware now, it's not really needed.
* | i915/i965 merge serer directories along lines for radeon/r200Dave Airlie2007-09-271-1/+13
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* Merge branch 'master' of git+ssh://[email protected]/git/mesa/mesa ↵Keith Whitwell2007-01-161-1/+4
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into vbo-0.2 Conflicts: src/mesa/array_cache/sources src/mesa/drivers/dri/i965/brw_context.c src/mesa/drivers/dri/i965/brw_draw.c src/mesa/drivers/dri/i965/brw_fallback.c src/mesa/drivers/dri/i965/brw_vs_emit.c src/mesa/drivers/dri/i965/brw_vs_tnl.c src/mesa/drivers/dri/mach64/mach64_context.c src/mesa/main/extensions.c src/mesa/main/getstring.c src/mesa/tnl/sources src/mesa/tnl/t_save_api.c src/mesa/tnl/t_save_playback.c src/mesa/tnl/t_vtx_api.c src/mesa/tnl/t_vtx_exec.c src/mesa/vbo/vbo_attrib.h src/mesa/vbo/vbo_exec_api.c src/mesa/vbo/vbo_save_api.c src/mesa/vbo/vbo_save_draw.c
| * Share code to lay out >= 945 style 2D mipmaps between i915tex and i965 drivers.Michel Dänzer2006-12-141-1/+4
| | | | | | | | Use the i965 version as it has some fixes over the i915tex version.
* | cleanup code, compiles with vbo changesKeith Whitwell2006-10-311-1/+0
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* | checkpoint - remove dead files, otherwise untestedKeith Whitwell2006-10-301-8/+0
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* Accelerate glBitmap with a color expand blit. Nice speedup for demosKeith Whitwell2006-10-051-0/+1
| | | | like 'fire' that display a help message or fps number this way.
* add accelerated glCopyPixels pathKeith Whitwell2006-09-201-0/+1
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* Basic facility for playing back captured aubfiles. Requires a smallKeith Whitwell2006-09-081-0/+1
| | | | | | hack to the drm to disable command verification on the cmd_buffer ioctl. Doesn't exactly replay as commands are normally delivered as batchbuffers but are captured and replayed as commands on the ring.
* Simplify the immediate and displaylist code. Treat VertexAttrib*ARBKeith Whitwell2006-09-061-1/+0
| | | | | as non-aliasing and cope with the >32 attributes that result, taking materials into account.
* Add Intel i965G/Q DRI driver.Eric Anholt2006-08-091-0/+97
This driver comes from Tungsten Graphics, with a few further modifications by Intel.