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* i915: check for depth region before accounting its buffer sizeDave Airlie2008-04-181-1/+2
| | | | fd.o bz #15573
* intel: fix _mesa_error ctx I introduced at lsat minuteDave Airlie2008-04-162-1/+34
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* intel/fake_bufmgr: Attempt to restrict references to objects in a ↵Dave Airlie2008-04-161-0/+31
| | | | | | | | | | | | | | | | | | | | | | | | batchbuffer > aperture size. So with compiz on Intel hw with fake bufmgr, opening 4 firefox windows at 1680x1050 and hitting alt-tab, could cause the batchbuffer to try and reference more than the 32MB of RAM allocated. Fix 1: Fix 1 is to pre-verify the list of buffers against the current batchbuffer and if it can't possibly fit in the aperture to flush the batchbuffer to the hardware and try again. If the buffers still can't fit well then you are hosed as I'm not sure there is a nice way to tell anyone. Fix 2: Next problem was that even with a simple check for total < aperture, we ran into fragmentation issues, this meant that half way down a set of buffers, we would fail as no blocks were available. Fix this by nuking the memory manager from orbit and letting it start again and relayout the blocks in a manner that fits. Fix 3: Finally the initial problem we were seeing was a memcpy to a NULL backing store. We seem to end up with a texture at some point that never gets mapped but ends up with data in it. compiz al-tab icons have this property. So I created a card dirty bit that memcpy's any buffer that is !static and is written to back to memory. This probably is wrong but it makes compiz work for now. Caveats: 965 support is still fail.
* i915: texture object's lod bias. fix bug #15192Xiang, Haihao2008-03-314-5/+25
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* [i915] don't use 4x4 filter for 1D shadowmapZou Nan hai2008-03-261-2/+7
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* intel: fix the issue "VBO: Cannot allocate memory for a BO" onXiang, Haihao2008-03-252-0/+13
| | | | 965 after merging intel_context.c from i915 and i965. fix bug# 15152.
* [i915] GL_DEPTH_TEXTURE_MODE fixZou Nan hai2008-03-201-3/+4
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* [i915] fix fragment.positionZou Nan hai2008-03-191-6/+21
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* [i915] Bug #13634: Fix bugs in 945 cube mipmap layout.Eric Anholt2008-03-181-15/+18
| | | | | | | | | | | | | The most egregious, and the one the bug report and failure in the cubemap demo were about was introduced with intel_mipmap_pitch_align(), where a "* 2" for the pitch calculation was lost. The base size < 32 case also failed to align, which may have caused problems with render to texture. Another bug would have broken 2x2/1x1 base mipmap levels by placing the data where the hardware wouldn't look for it. Other bugs remain with the layout of the small mipmap faces (hardware looks for them in X,Y,Z,-X,-Y,-Z order along the bottom row, but we lay them out X,-X,Y,-Y,Z,-Z).
* [i915] Add comments about how cube texture layout works.Eric Anholt2008-03-181-2/+107
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* [i915] Move miptree layout code into separate functions per target.Eric Anholt2008-03-181-258/+285
| | | | Also clean up some other miscellaneous formatting nits while I'm at it.
* [945] Remove conditional in 945 3D mipmap layout checking for cube layout.Eric Anholt2008-03-181-4/+3
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* intel: fix abort issue with shadowtex demo when useXiang, Haihao2008-03-141-1/+1
| | | | DEPTH_STENCIL texture. (bug#14952).
* [i965] multiple rendering target supportZou Nan hai2008-03-132-6/+8
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* intel: Add missing include file to silence last couple of warnings.Kristian Høgsberg2008-02-251-0/+1
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* intel: Initialize color and spec arrays in LOCAL_VARS macro.Kristian Høgsberg2008-02-251-4/+4
| | | | | Avoids spamming compilation output with tons of warnings about use of possibly uninitialized variables.
* intel: Merge intel_context.c from i915 and i965.Kristian Høgsberg2008-02-223-1/+45
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* Merge {i915,i965}/intel_context.h as intel/intel_context.hKristian Høgsberg2008-02-222-1315/+1
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* Use drm_i915_sarea instead of drmI830Sarea and remove i830_common.hAlan Hourihane2008-02-222-4/+3
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* Add E7221 variant to i915.Adam Jackson2008-02-151-0/+4
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* i915: set fogcoord to (f,0,0,1). fix #10788 issue on 915.Xiang, Haihao2008-02-151-1/+1
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* Hook up i915 driver to new DRI2 infrastructure.Kristian Høgsberg2008-02-141-32/+43
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* [intel] Fix 965 rendering with non-TTM by merging intel_ioctl between 915/965.Eric Anholt2008-02-133-174/+8
| | | | | | The 965 path wasn't setting pClipRects for batch submission since it didn't want kernel cliprect handling before. The 915 path also grew the INTEL_NO_HW=1 option for testing just driver overhead.
* [915] Fix COS function using same plan as SIN.Eric Anholt2008-02-061-35/+63
| | | | The previous COS function failed badly outside of [-pi/2, pi/2].
* [915] Use a quartic term to improve the accuracy of SIN results.Eric Anholt2008-02-061-23/+54
| | | | | This is described in the link in the comment, and is the same technique that r300 uses.
* [915] Fix fp SIN function, and use a quadratic approximation instead of Taylor.Eric Anholt2008-02-061-42/+57
| | | | | | | | | | | The Taylor series notably fails at producing sin(pi) == 0, which leads to discontinuity every 2*pi. The quadratic gets us sin(pi) == 0 behavior, at the expense of going from 2.4% THD with working Taylor series to 3.8% THD (easily seen on comparative graphs of the two). However, our previous implementation was producing sin(pi) < -1 and worse, so any reasonable approximation is an improvement. This also fixes the repeating behavior, where the previous implementation would repeat sin(x) for x>pi as sin(x % pi) and the opposite for x < -pi.
* [intel] Clean up references to screen buffer metrics.Kristian Høgsberg2008-01-222-72/+3
| | | | | | The screen wide info such as pitch and cpp are obsoleted by the FBO changes, so clean up the last few references to those, except for setting up the legacy screen regions.
* [intel] Make the no_rast option be standard driconf instead of INTEL_NO_RAST.Eric Anholt2008-01-171-1/+1
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* [i915] Fix driver from cliprects changes, and clean up state emission.Eric Anholt2008-01-174-101/+26
| | | | | | | | | | The fix for pageflipping with cliprects ended up causing a batch flush at an inopportune time, which is fixed by moving it up. Additionally, the recovery code for handling batch wraps at bad times is replaced by just checking for the space up front, and using a no_batch_wrap assert like on 965 to make sure that we weren't wrong about how much space that was.
* [i915] Fix recursive lock hang in intelContendedLock handling.Eric Anholt2008-01-141-2/+2
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* [intel] Add more cliprect modes to cover other meanings for batch emits.Eric Anholt2008-01-105-28/+26
| | | | | | | | | | | | | | | The previous change gave us only two modes, one which looped over the batch per cliprect (3d drawing) and one that didn't (state updeast). However, we really want 4: - Batch doesn't care about cliprects (state updates) - Batch needs DRAWING_RECTANGLE looping per cliprect (3d drawing) - Batch needs to be executed just once (region fills, copies, etc.) - Batch already includes cliprect handling, and must be flushed by unlock time (copybuffers, clears). All callers should now be fixed to use one of these states for any batchbuffer emits. Thanks to Keith Whitwell for pointing out the failure.
* [intel] Simplify intelCreateBuffer() a bit.Kristian Høgsberg2008-01-091-13/+13
| | | | | | Drop a bunch of unused arguments from intel_create_renderbuffer() and introduce intel_renderbuffer_set_region() to set the region for a renderbuffer.
* [intel] Rename lost_hardware vtbl entry to new_batch.Eric Anholt2008-01-094-16/+10
| | | | | | | Both drivers have ended up relying on lost_hardware being called after each batch buffer, so update the name. This removes one of the calls on 965 whic h was outside of the batchbuffer handling code and just duplicating what had already happened through batchbuffer handling.
* [intel] Clean up cliprect handling in intel drivers.Eric Anholt2008-01-091-2/+2
| | | | | | | | | In particular, batch buffers are no longer flushed when switching from CLIPRECTS to NO_CLIPRECTS or vice versa, and 965 just uses DRM cliprect handling for primitives instead of trying to sneak in its own to avoid the DRM stuff. The disadvantage is that we will re-execute state updates per cliprect, but the advantage is that we will be able to accumulate larger batch buffers, which were proving to be a major overhead.
* [intel] Remove the dead intel->need_flush member.Eric Anholt2008-01-091-1/+0
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* i915: Keith Whitwell's swizzling TEX patch. fix #8283Xiang, Haihao2008-01-074-13/+83
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* Replace gl_framebuffer's _ColorDrawBufferMask with _ColorDrawBufferIndexesBrian2008-01-061-3/+1
| | | | | | | Each array element is now a BUFFER_x token rather than a BUFFER_BIT_x bitmask. The number of active color buffers is specified by _NumColorDrawBuffers. This builds on the previous DrawBuffer changes and will help with drivers implementing GL_ARB_draw_buffers.
* Simplify ctx->_NumColorDrawBuffers, _ColorDrawBuffers and fix bug 13835.Brian2008-01-061-1/+1
| | | | | | | | | | | These fields are no longer indexed by shader output. Now, we just have a simple array of renderbuffer pointers. If the shader writes to gl_FragData[i], send those colors to the N _ColorDrawBuffers. Otherwise, replicate the single gl_FragColor (or the fixed-function color) to the N _ColorDrawBuffers. A few more changes and simplifications can follow from this...
* i915: don't validate PS program when falling back to softwareXiang, Haihao2008-01-041-1/+2
| | | | rendering. fix #12786
* fix fd.o bug #13761Zou Nan hai2008-01-031-2/+2
| | | | MRD computation is now changed in mesa core
* i915: Needn't adjust pixel centers. fix #12944Xiang, Haihao2008-01-022-4/+4
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* i915: apply commit a0a5e8cfc04c14873441b50f7d594ef11806b9a8 from 965.Xiang, Haihao2007-12-253-1/+28
| | | | fix #11925
* fix GL_LINE_LOOP with drivers using own render pipeline stage (#12410, #13527)Roland Scheidegger2007-12-221-1/+1
| | | | | | primitive needs to include the begin/end flags (broken since vbo-0.2). Should fix missing first/last line segment on gamma, i810, i915, mga, r200, radeon, s3v, savage, unichrome (r300 already correct). Tested on r200, fixes #13527.
* [intel] Move some pixel path support from drivers to shared.Eric Anholt2007-12-214-951/+3
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* intel: cast a pointer to unsigned long, avoid potential error.Xiang, Haihao2007-12-211-1/+1
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* [intel] Fix and reenable (software) SGIS_generate_mipmapEric Anholt2007-12-201-1/+1
| | | | | | | The core problem was that _mesa_generate_mipmap was not respecting RowStride of the source image. Additionally, the intel private data associated with the images (level and face) was not being initialized for the _mesa_generate_mipmap-generated images.
* [i915] Move meta_draw_quad into the vtbl with other meta operations.Eric Anholt2007-12-205-31/+27
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* i915: avoid dead lock in intel_meta_draw_poly. fix #13696Xiang, Haihao2007-12-201-2/+6
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* [915] Free dri_bufmgr after mesa context data.Eric Anholt2007-12-181-2/+2
| | | | Fixes a crash when buffer objects are left around until context destroy.
* [915] Make polygon stipple use pre-unpacked pixel data.Eric Anholt2007-12-181-1/+7
| | | | This fixes a crash when stippling using data from a PBO.
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