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* i915: Remove unnecessary headers.Vinson Lee2010-01-302-2/+0
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* i915: Remove unused initial and current state, now that there's nothing else.Eric Anholt2010-01-286-22/+10
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* intel: Remove long-disabled meta readpixels, and associated meta support.Eric Anholt2010-01-289-1042/+20
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* Merge branch 'mesa_7_7_branch'Brian Paul2010-01-255-13/+0
|\ | | | | | | | | | | | | | | | | | | | | Conflicts: src/mesa/drivers/dri/intel/intel_screen.c src/mesa/drivers/dri/intel/intel_swapbuffers.c src/mesa/drivers/dri/r300/r300_emit.c src/mesa/drivers/dri/r300/r300_ioctl.c src/mesa/drivers/dri/r300/r300_tex.c src/mesa/drivers/dri/r300/r300_texstate.c
| * i915: Remove unnecessary headers.Vinson Lee2010-01-225-13/+0
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* | dri: Remove unnecessary glapi headers.Chia-I Wu2010-01-212-4/+0
| | | | | | | | They are not used at all.
* | intel: Remove leftover symlinks from DRI1 removal.Eric Anholt2010-01-071-1/+0
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* | Merge branch 'remove-intel-dri1'Kristian Høgsberg2010-01-058-89/+52
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * remove-intel-dri1: intel: intelScreenContext() is no longer used intel: Remove remaining dri2.enabled tests intel: Drop more cliprect bookkeeping intel: Remove struct intel_framebuffer intel: Remove client-side vblank code intel: Drop intelWindowMoved() intel: Drop batchbuffer cliprect_mode tracking intel: Drop DRI1 static regions intel: Use depth buffer from ctx.DrawBuffer in copypix_src_region() intel: Drop LOCK/UNLOCK_HARDWARE() intel: Drop DRI1 SwapBuffer implementation intel: Drop DRI1 CopySubBuffer implementation intel: Drop DRI1 support Push __driDriverExtensions out of dri_util.c and into the drivers Remove leftover __DRI{screen,drawable,context}Private references Check for libdrm_$chipset.pc when needed
| * | intel: Drop more cliprect bookkeepingKristian Høgsberg2010-01-042-60/+32
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| * | intel: Remove client-side vblank codeKristian Høgsberg2010-01-041-1/+0
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| * | intel: Drop batchbuffer cliprect_mode trackingKristian Høgsberg2010-01-043-23/+14
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| * | Remove leftover __DRI{screen,drawable,context}Private referencesKristian Høgsberg2010-01-044-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | As part of the DRI driver interface rewrite I merged __DRIscreenPrivate and __DRIscreen, and likewise for __DRIdrawablePrivate and __DRIcontextPrivate. I left typedefs in place though, to avoid renaming all the *Private use internal to the driver. That was probably a mistake, and it turns out a one-line find+sed combo can do the mass rename. Better late than never.
| * | Check for libdrm_$chipset.pc when neededKristian Høgsberg2010-01-041-1/+2
| | | | | | | | | | | | | | | | | | This adds missing pkg-config lookup for intel and moves the radeon lookup into a case...esac so it's only looked up when one or more of the radeon drivers are enabled.
* | | mesa: make texture BorderColor a union of float/int/uintBrian Paul2010-01-042-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | When we have integer-valued texture formats, the texture border color must also store integer and uint values. With GL 3.0, the new glTexParameterIiv() and glTexParameterIuiv() functions can set the border color to int or uint values.
* | | Merge branch 'mesa_7_7_branch'Brian Paul2010-01-041-3/+4
|\ \ \ | |/ / |/| / | |/ | | | | | | | | | | Conflicts: docs/relnotes.html src/gallium/drivers/llvmpipe/lp_tex_sample_c.c src/gallium/drivers/r300/r300_cs.h src/mesa/drivers/dri/i965/brw_wm_surface_state.c src/mesa/main/enums.c
| * i915: Use _MaxLevel on principle in texture setup.Eric Anholt2010-01-041-3/+4
| | | | | | | | | | | | It was OK before because we proceed to clamp the value to hardware limits, but given that other use of MaxLevel has been a trap, let's avoid it.
* | Merge branch 'mesa_7_7_branch'Brian Paul2009-12-312-3/+3
|\| | | | | | | | | | | | | | | Conflicts: configs/darwin src/gallium/auxiliary/util/u_clear.h src/gallium/state_trackers/xorg/xorg_exa_tgsi.c src/mesa/drivers/dri/i965/brw_draw_upload.c
| * intel: Silence compiler warnings.Vinson Lee2009-12-281-2/+2
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| * Merge branch 'mesa_7_6_branch' into mesa_7_7_branchBrian Paul2009-12-271-1/+1
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: src/gallium/auxiliary/util/u_network.c src/gallium/auxiliary/util/u_network.h src/gallium/drivers/i915/i915_state.c src/gallium/drivers/trace/tr_rbug.c src/gallium/state_trackers/vega/bezier.c src/gallium/state_trackers/vega/vg_context.c src/gallium/state_trackers/xorg/xorg_crtc.c src/gallium/state_trackers/xorg/xorg_driver.c src/gallium/winsys/xlib/xlib_brw_context.c src/mesa/main/mtypes.h
| | * i915: Fix assert.Vinson Lee2009-12-261-1/+1
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* | | intel: Replace some gen3 IS_* checks with context structure usage.Eric Anholt2009-12-222-3/+3
| | | | | | | | | | | | Shaves 400 bytes or so from i915_dri.so.
* | | i915: Fix use of uninitialized variable in OPCODE_NOISE stub.Eric Anholt2009-12-221-1/+1
| | | | | | | | | | | | | | | | | | We don't actually care which register is used since we're just swizzling (0,0,0,0), but it should be a valid variable number. Detected by clang.
* | | mesa: Replace CLAMP_SELF() macro with more obvious CLAMP() usage.Eric Anholt2009-12-222-4/+4
| | | | | | | | | | | | | | | The same code is generated, and readers and static analyzers are happier.
* | | Merge branch 'mesa_7_7_branch'Brian Paul2009-12-211-11/+7
|\| | | | | | | | | | | | | | | | | Conflicts: src/mesa/main/version.h src/mesa/state_tracker/st_atom_shader.c
| * | i915: Fix GL_TEXTURE_MAX_LEVEL support (piglit levelclamp test).Eric Anholt2009-12-181-1/+6
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| * | i915: Clean up some unnecessary x/y miptree code.Eric Anholt2009-12-181-10/+1
| | | | | | | | | | | | | | | | | | The base of the texture is always the base of the miptree. If it wasn't, we'd have issues with this code due to miptrees not walking the same direction for all LODs.
* | | Merge branch 'mesa_7_7_branch'Brian Paul2009-12-115-12/+7
|\| | | | | | | | | | | | | | | | | Conflicts: src/gallium/state_trackers/xorg/xorg_xv.c src/mesa/drivers/dri/intel/intel_span.c
| * | Merge branch 'mesa_7_6_branch' into mesa_7_7_branchBrian Paul2009-12-111-0/+1
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| | * i915: Add missing break statement in i915_debug_packet.Vinson Lee2009-12-101-0/+1
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| * | intel: Remove ARGB internal_format == GL_RGB hacksIan Romanick2009-12-102-8/+2
| | | | | | | | | | | | | | | Now that XRGB is supported, we don't need to hack around cases of an RGBA format buffer with an internal format of GL_RGB.
| * | intel: Axe intel_renderbuffer::texformatIan Romanick2009-12-102-4/+4
| | | | | | | | | | | | | | | Since the texformat branch merge, the value of intel_renderbuffer::texformat is just a copy of gl_renderbuffer::Format.
* | | intel: Attempt to fix up after "Update vertex texture code."Eric Anholt2009-12-101-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MaxCombinedTextureImageUnits is the total number of samplers that can be bound between vertex, geometry, and fragment, not 0. This should report the correct value on 965 now. Other DRI drivers may also need updating if their MaxVertexTextureImageUnits != 0 (for example, if using the sw vertex pipeline). It's not clear to me if there's going to be a valid value for this limit other than MaxTextureImageUnits + MaxVertexTextureImageUnits (+ MaxGeometryTextureImageUnits eventually). If not, then we should probably just move this into the core at Get time. Bug #25518 (wine regression). Fixes piglit vp-combined-image-units.
* | | Merge commit 'origin/mesa_7_7_branch'Keith Whitwell2009-12-012-1/+32
|\| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: src/gallium/drivers/svga/svga_screen_texture.c src/gallium/state_trackers/xorg/xorg_composite.c src/gallium/state_trackers/xorg/xorg_exa.c src/gallium/state_trackers/xorg/xorg_renderer.c src/gallium/state_trackers/xorg/xorg_xv.c src/mesa/main/texgetimage.c src/mesa/main/version.h
| * | Merge branch 'mesa_7_6_branch' into mesa_7_7_branchIan Romanick2009-11-302-1/+32
| |\| | | | | | | | | | | | | | | | | | | Conflicts: progs/util/shaderutil.c src/mesa/drivers/dri/r600/r600_context.c src/mesa/main/version.h
| | * i915: Actually put i915PointParameterfv in the driver function table. Duh.Ian Romanick2009-11-301-0/+1
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| | * i915: Fallback bit define missed on previous commitIan Romanick2009-11-291-0/+1
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| | * i915: Round point sizes instead of truncate.Ian Romanick2009-11-291-1/+1
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| | * i915: Enable point sprite coordinate generationIan Romanick2009-11-291-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support still isn't completely correct, but it's better. piglit point-sprite now passes. However, glean's pointSprite test fails. In that test the texture on the sprite is somehow inverted as though GL_POINT_SPRITE_COORD_ORIGIN were set to GL_LOWER_LEFT. i915 hardware shouldn't be able to do that! I believe there are also problems when not all texture units have GL_COORD_REPLACE set. The hardware enable seems to be all or nothing. Fixes bug #25313.
| | * i915: Fix driver for the miptree x/y offset changes.Eric Anholt2009-10-272-6/+20
| | | | | | | | | | | | Bug #24734.
* | | intel: Remove our special color packing macros and just use colormac.h.Eric Anholt2009-11-192-13/+14
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* | | intel: Consistently use no_batch_wrap in intel_context struct.Eric Anholt2009-11-192-6/+0
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* | | i915: Remove dead meta_draw_quad code.Eric Anholt2009-11-191-78/+0
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* | | tnl: Replace deprecated TexCoordPtr with AttribPtr[_TNL_ATTRIB_TEX*]Eric Anholt2009-11-192-2/+2
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* | intel: Use PIPE_CONTROL on gen4 hardware for doing pipeline flushing.Eric Anholt2009-11-062-17/+0
| | | | | | | | | | | | This should do all the things that MI_FLUSH did, but it can be pipelined so that further rendering isn't blocked on the flush completion unless necessary.
* | intel: avoid unnecessary front buffer flushing/updatingBrian Paul2009-11-031-0/+1
| | | | | | | | | | | | | | | | | | | | | | Before, if we just called glXMakeCurrent() and didn't render anything we'd still trigger a flushFrontBuffer() call. Now only set the intel->front_buffer_dirty field at state validation time just before we draw something. NOTE: additional calls to intel_check_front_buffer_rendering() might be needed if I missed some rendering paths.
* | intel: update intel_create_renderbuffer(format), add XRGB supportBrian Paul2009-10-294-0/+6
| | | | | | | | | | | | | | | | Pass a gl_format to intel_create_renderbuffer() instead of GLenum. Add cases for MESA_FORMAT_XRGB8888 textures and renderbuffers. However, we don't yet create any renderbuffers or textures with that format. It seems the default alpha value is zero instead of one. Need to investigate that first.
* | i915: Fix 1D texture mapping in the t coordinate.Eric Anholt2009-10-291-0/+6
| | | | | | | | Fixes piglit tex1d-2dborder test.
* | i915: Correct and make use of the defines for 32-bit depth texture modes.Eric Anholt2009-10-292-4/+9
| | | | | | | | | | Previously, S8_Z24 depth textures would always be treated as intensity. Fixes piglit depth-tex-modes.
* | i915: Implement min/max LOD clamping with the hardware.Eric Anholt2009-10-291-4/+8
| | | | | | | | | | | | | | This gets us expected behavior for clamping between mipmap levels, and avoids relayout of textures for doing clamping. Fixes piglit lodclamp-between.
* | Merge branch 'texformat-rework'Brian Paul2009-10-285-14/+9
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: src/mesa/drivers/dri/radeon/radeon_fbo.c src/mesa/drivers/dri/s3v/s3v_tex.c src/mesa/drivers/dri/s3v/s3v_xmesa.c src/mesa/drivers/dri/trident/trident_context.c src/mesa/main/debug.c src/mesa/main/mipmap.c src/mesa/main/texformat.c src/mesa/main/texgetimage.c
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