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* intel/isl: move tiled_memcpy static libs from i965 to islTapani Pälli2019-01-1010-5/+1353
| | | | | | | | | | | | | | Patch moves intel_tiled_memcpy[_sse41] libraries to isl, renames some functions and types and makes the required build system changes for meson, automake and Android. No functional changes are introduced. v2: code cleanups, move isl_get_memcpy_type to i965 (Jason) v3: move isl_mem_copy_fn to priv header, cleanups (Jason, Dylan) Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Dylan Baker <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965: Compile fp64 software routines and lower double-opsMatt Turner2019-01-091-22/+70
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* intel/compiler: Heap-allocate temporary storageMatt Turner2019-01-091-3/+5
| | | | | | | | Shaders containing software implementations of double-precision operations can be very large such that we cannot stack-allocate an array of grf_count*16. Reviewed-by: Kenneth Graunke <[email protected]>
* intel/compiler: Expand size of the 'nr' fieldMatt Turner2019-01-091-4/+3
| | | | | | | | | | | Shaders containing software implementations of double-precision operations can be very large such that we have more the 2^16 virtual registers during optimization. Move the 'nr' field to the union containing the immediate storage and expand it to 32-bits. Reviewed-by: Kenneth Graunke <[email protected]>
* intel/compiler: Prevent warnings in the following patchMatt Turner2019-01-0911-36/+38
| | | | | | | | | | The next patch replaces an unsigned bitfield with a plain unsigned, which triggers gcc to begin warning on signed/unsigned comparisons. Keeping this patch separate from the actual move allows bisectablity and generates no additional warnings temporarily. Reviewed-by: Kenneth Graunke <[email protected]>
* intel/compiler: Rearrange code to avoid future problemsMatt Turner2019-01-091-3/+4
| | | | | | | | A follow on commit will move nr to the same union as the immediate data, so we should assert these invariants before we overwrite the nr field. Reviewed-by: Kenneth Graunke <[email protected]>
* intel/compiler: Avoid false positive assertionsMatt Turner2019-01-091-6/+6
| | | | | | | | | | | A follow on patch will move the 'nr' field to the union containing the immediate field, so prepare by checking that we're only testing these assertions if the .file is correct. The assertions with != ARF were kind of silly to begin with because the <128 check is specifically only for things in the GRF. Reviewed-by: Kenneth Graunke <[email protected]>
* intel/compiler: Split 64-bit MOV-indirects if neededMatt Turner2019-01-091-1/+2
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* intel/compiler: Lower 64-bit MOV/SEL operationsMatt Turner2019-01-091-1/+49
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* intel/fs: Remove FS_OPCODE_UNPACK_HALF_2x16_SPLIT opcodes.Francisco Jerez2019-01-096-47/+4
| | | | | | | | These are broken on a future platform, but it turns out we don't need to fix them, since they're just type-converting moves with strided source. Kill them. Reviewed-by: Iago Toral Quiroga <[email protected]>
* intel/fs: Remove nasty open-coded CHV/BXT 64-bit workarounds.Francisco Jerez2019-01-092-145/+12
| | | | Reviewed-by: Iago Toral Quiroga <[email protected]>
* intel/fs: Remove existing lower_conversions pass.Francisco Jerez2019-01-095-139/+1
| | | | | | It's redundant with the functionality provided by lower_regioning now. Reviewed-by: Iago Toral Quiroga <[email protected]>
* intel/fs: Introduce regioning lowering pass.Francisco Jerez2019-01-096-19/+418
| | | | | | | | | | | | | | | | | This legalization pass is meant to handle situations where the source or destination regioning controls of an instruction are unsupported by the hardware and need to be lowered away into separate instructions. This should be more reliable and future-proof than the current approach of handling CHV/BXT restrictions manually all over the visitor. The same mechanism is leveraged to lower unsupported type conversions easily, which obsoletes the lower_conversions pass. v2: Give conditional modifiers the same treatment as predicates for SEL instructions in lower_dst_modifiers() (Iago). Special-case a couple of other instructions with inconsistent conditional mod semantics in lower_dst_modifiers() (Curro). Reviewed-by: Iago Toral Quiroga <[email protected]>
* intel/fs: Constify fs_inst::can_do_source_mods().Francisco Jerez2019-01-092-2/+2
| | | | Reviewed-by: Iago Toral Quiroga <[email protected]>
* intel/fs: Respect CHV/BXT regioning restrictions in copy propagation pass.Francisco Jerez2019-01-092-0/+38
| | | | | | | | | | | | | Currently the visitor attempts to enforce the regioning restrictions that apply to double-precision instructions on CHV/BXT at NIR-to-i965 translation time. It is possible though for the copy propagation pass to violate this restriction if a strided move is propagated into one of the affected instructions. I've only reproduced this issue on a future platform but it could affect CHV/BXT too under the right conditions. Cc: [email protected] Reviewed-by: Iago Toral Quiroga <[email protected]>
* intel/eu/gen7: Fix brw_MOV() with DF destination and strided source.Francisco Jerez2019-01-091-7/+4
| | | | | | | | | I triggered this bug while prototyping code for a future platform on IVB. Could be a problem today though if a strided move is copy-propagated into a type-converting move with DF destination. Cc: [email protected] Reviewed-by: Iago Toral Quiroga <[email protected]>
* intel/fs: Fix bug in lower_simd_width while splitting an instruction which ↵Francisco Jerez2019-01-091-2/+5
| | | | | | | | | | | | | was already split. This seems to be a problem in combination with the lower_regioning pass introduced by a future commit, which can modify a SIMD-split instruction causing its execution size to become illegal again. A subsequent call to lower_simd_width() would hit this bug on a future platform. Cc: [email protected] Reviewed-by: Iago Toral Quiroga <[email protected]>
* intel/fs: Implement quad swizzles on ICL+.Francisco Jerez2019-01-093-18/+97
| | | | | | | | | | | | | Align16 is no longer a thing, so a new implementation is provided using Align1 instead. Not all possible swizzles can be represented as a single Align1 region, but some fast paths are provided for frequently used swizzles that can be represented efficiently in Align1 mode. Fixes ~90 subgroup quad swap Vulkan CTS tests. Cc: [email protected] Reviewed-by: Iago Toral Quiroga <[email protected]>
* intel/fs: Handle source modifiers in lower_integer_multiplication().Francisco Jerez2019-01-092-2/+37
| | | | | | | | | | | | lower_integer_multiplication() implements 32x32-bit multiplication on some platforms by bit-casting one of the 32-bit sources into two 16-bit unsigned integer portions. This can give incorrect results if the original instruction specified a source modifier. Fix it by emitting an additional MOV instruction implementing the source modifiers where necessary. Cc: [email protected] Reviewed-by: Iago Toral Quiroga <[email protected]>
* anv/pipeline: remove unnecessary null-pointer checkAndrii Simiklit2019-01-091-4/+2
| | | | | | | | | | | | Looks like it is impossible that 'last' variable is a null because at least the get_vs_prog_data shouldn't return a null pointer. So this check is unnecessary starts from commit: 99d497c5b691 "anv/pipeline: Replace get_fs_input_map with ..." This small issue is found by cppcheck. Signed-off-by: Andrii Simiklit <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* anv: drop unneeded KHR suffixEric Engestrom2019-01-0813-54/+54
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Acked-by: Jason Ekstrand <[email protected]>
* nir: rename global/local to private/function memoryKarol Herbst2019-01-082-7/+7
| | | | | | | | | | | | | | | | | | the naming is a bit confusing no matter how you look at it. Within SPIR-V "global" memory is memory accessible from all threads. glsl "global" memory normally refers to shader thread private memory declared at global scope. As we already use "shared" for memory shared across all thrads of a work group the solution where everybody could be happy with is to rename "global" to "private" and use "global" later for memory usually stored within system accessible memory (be it VRAM or system RAM if keeping SVM in mind). glsl "local" memory is memory only accessible within a function, while SPIR-V "local" memory is memory accessible within the same workgroup. v2: rename local to function as well v3: rename vtn_variable_mode_local as well Signed-off-by: Karol Herbst <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* anv: flush fast clear colors into compressed surfacesLionel Landwerlin2019-01-081-0/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the following scenario : 1. Create image format R8G8B8A8_UNORM 2. Create image view format R8G8B8A8_SRGB 3. Clear the view through a sub pass to a particular color 4. Barrier on the image to from color attachment to source transfer 5. Copy the image into a linear buffer to check the content The step 4 resolving the clear color is unaware of the SRGB format of the view, because the blorp resolve operations operate on images the color associated with the resolve will not operate on SRGB format but UNORM. Leading to the wrong color being written into surfaces. This change forces a clear color resolve at the end of the render pass so following resolves won't have to deal with the clear color with a format that doesn't match the image's format. On gfxbench vulkan_5_normal 1280x720, this appear to cost us ~0.5fps, from 49.316 down to 48.949. v2: Only fast clear resolve when image & view have different formats (Lionel) v3: Update warning (Jason) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108911 Signed-off-by: Lionel Landwerlin <[email protected]> Suggested-by: Jason Ekstrand <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Cc: [email protected]
* anv: explictly specify format for blorp ccs/mcs opLionel Landwerlin2019-01-083-16/+30
| | | | | | | | | | | | | | Resolve operations can happen when dealing with view (begin/end subpasses) in which case the view's format needs to apply, not the image's format. v2: Relayout arguments of a ccs_op() call (Jason) Signed-off-by: Lionel Landwerlin <[email protected]> Suggested-by: Jason Ekstrand <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108911 Cc: [email protected]
* anv: Sort properties and features switch statementsJason Ekstrand2019-01-071-42/+42
| | | | Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* spirv: Sort supported capabilitiesJason Ekstrand2019-01-071-9/+9
| | | | Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* anv: Enable the new deref-based UBO/SSBO pathJason Ekstrand2019-01-082-1/+23
| | | | | Reviewed-by: Alejandro Piñeiro <[email protected]> Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* spirv: Add support for using derefs for UBO/SSBO accessJason Ekstrand2019-01-081-0/+1
| | | | | | | | | For now, it's hidden behind a cap. Hopefully, we can eventually drop that along with all the manual offset code in spirv_to_nir. Reviewed-by: Alejandro Piñeiro <[email protected]> Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Tested-by: Bas Nieuwenhuizen <[email protected]>
* spirv: Add explicit pointer typesJason Ekstrand2019-01-081-0/+4
| | | | | | | | Instead of baking in uvec2 for UBO and SSBO pointers and uint for push constant and shared memory pointers, make it configurable. Reviewed-by: Alejandro Piñeiro <[email protected]> Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* nir: Move propagation of cast derefs to a new nir_opt_deref passJason Ekstrand2019-01-081-1/+1
| | | | | | | | | We're going to want to do more deref optimizations going forward and this gives us a central place to do them. Also, cast propagation will get a bit more complicated with the addition of ptr_as_array derefs. Reviewed-by: Alejandro Piñeiro <[email protected]> Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* glsl_type: Add support for explicitly laid out matrices and arraysJason Ekstrand2019-01-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | SPIR-V allows for matrix and array types to be decorated with explicit byte stride decorations and matrix types to be decorated row- or column-major. This commit adds support to glsl_type to encode this information. Because this doesn't work nicely with std430 and std140 alignments, we add asserts to ensure that we don't use any of the std430 or std140 layout functions with explicitly laid out types. In SPIR-V, the layout information for matrices is applied to the parent struct member instead of to the matrix type itself. However, this is gets rather clumsy when you're walking derefs trying to compute offsets because, the moment you hit a matrix, you have to crawl back the deref chain and find the struct. Instead, we take the same path here as we've taken in spirv_to_nir and put the decorations on the matrix type itself. This also subtly adds support for strided vector types. These don't come up in SPIR-V directly but you can get one as the result of taking a column from a row-major matrix or a row from a column-major matrix. Reviewed-by: Alejandro Piñeiro <[email protected]>
* anv/apply_pipeline_layout: Set the cursor in lower_res_reindex_intrinsicJason Ekstrand2019-01-081-0/+2
| | | | | | | | | | | | | The loop through instructions doesn't set the cursor for us so unless we set it somewhere, we may end up emitting instructions in the wrong place. The only reason why we haven't been bitten by this in the past is that it only happens in a few variable pointers cases and the CTS tests for those don't use much control flow so things were getting emitted in the correct order by accident. Cc: [email protected] Reviewed-by: Alejandro Piñeiro <[email protected]> Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* anv/android: Do not reject storage images.Bas Nieuwenhuizen2019-01-071-8/+2
| | | | | | | | | | | | | | | | | We do the ImageFormatProperties check already, and rejecting an usage flag when both ImageFormatProperties and the WSI (which is Android) support it is not allowed. Intel does support storage for some of the support WSI formats, such as R8G8B8A8_UNORM, and looking at the ISL_SURF_USAGE_DISABLE_AUX_BIT, the imported images do not have any form of compression that would prevent this fix. v2: Also consider STORAGE bit for Gralloc usage bits. (From Kevin Strasser <[email protected]>) Fixes: 053d4c328fa "anv: Implement VK_ANDROID_native_buffer (v9)" Reviewed-by: Tapani Pälli <[email protected]>
* intel/blorp: Be more conservative about copying clear colorsJason Ekstrand2019-01-041-3/+6
| | | | | | | | | | | | In 92eb5bbc68d7324 we attempted to avoid copying clear colors whenever we weren't doing a resolve. However, this broke MSAA resolves because we need the clear color in the source. This patch makes blorp much more conservative such that it only avoids the clear color copy if either aux_usage == NONE or it's explicitly doing a fast-clear. Fixes: 92eb5bbc68d7 "intel/blorp: Only copy clear color when doing..." Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107728 Reviewed-by: Rafael Antognolli <[email protected]>
* intel/blorp: emit VF caching workaround before 3DSTATE_VERTEX_BUFFERSLionel Landwerlin2019-01-041-2/+2
| | | | | | | | | Probably no difference but it's nice to have i965 & blorp emit things in the same order. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* nir: rename nir_link_constant_varyings() nir_link_opt_varyings()Timothy Arceri2019-01-021-1/+1
| | | | | | | | | | The following patches will add support for an additional optimisation so this function will no longer just optimise varying constants. Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* anv/autotools: make sure tests link with -msse2Erik Faye-Lund2018-12-311-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Without this, I get the following error when building the tests with autotools on i686: ---8<--- src/intel/common/gen_clflush.h: In function ‘gen_clflush_range’: src/intel/common/gen_clflush.h:37:7: warning: implicit declaration of function ‘__builtin_ia32_clflush’; did you mean ‘__builtin_ia32_pause’? [-Wimplicit-function-declaration] __builtin_ia32_clflush(p); ^~~~~~~~~~~~~~~~~~~~~~ __builtin_ia32_pause src/intel/common/gen_clflush.h: In function ‘gen_flush_range’: src/intel/common/gen_clflush.h:45:4: warning: implicit declaration of function ‘__builtin_ia32_mfence’; did you mean ‘__builtin_ia32_fnclex’? [-Wimplicit-function-declaration] __builtin_ia32_mfence(); ^~~~~~~~~~~~~~~~~~~~~ __builtin_ia32_fnclex ---8<--- The erros are generated for each of these files: - mesa/src/intel/vulkan/tests/state_pool_no_free.c - mesa/src/intel/vulkan/tests/state_pool.c - mesa/src/intel/vulkan/tests/block_pool_no_free.c - mesa/src/intel/vulkan/tests/state_pool_free_list_only.c This is obviously because gen_clflush.h contains code that uses intrinsics that are only available with SSE3. Since the driver already uses SSE3, it seems reasonable to add this to the tests as well. Signed-off-by: Erik Faye-Lund <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Acked-by: Eric Engeström <[email protected]>
* anv/meson: make sure tests link with -msse2Erik Faye-Lund2018-12-311-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Without this, I get the following error when building the tests using meson on i686: ---8<--- In file included from ../../../mesa/src/intel/vulkan/anv_private.h:46, from ../../../mesa/src/intel/vulkan/tests/state_pool_no_free.c:26: ../../../mesa/src/intel/common/gen_clflush.h: In function ‘gen_clflush_range’: ../../../mesa/src/intel/common/gen_clflush.h:37:7: error: implicit declaration of function ‘__builtin_ia32_clflush’; did you mean ‘__builtin_ia32_pause’? [-Werror=implicit-function-declaration] __builtin_ia32_clflush(p); ^~~~~~~~~~~~~~~~~~~~~~ __builtin_ia32_pause ../../../mesa/src/intel/common/gen_clflush.h: In function ‘gen_flush_range’: ../../../mesa/src/intel/common/gen_clflush.h:45:4: error: implicit declaration of function ‘__builtin_ia32_mfence’; did you mean ‘__builtin_ia32_fnclex’? [-Werror=implicit-function-declaration] __builtin_ia32_mfence(); ^~~~~~~~~~~~~~~~~~~~~ __builtin_ia32_fnclex ---8<--- The errors are generated for each of these files: - mesa/src/intel/vulkan/tests/state_pool_no_free.c - mesa/src/intel/vulkan/tests/state_pool.c - mesa/src/intel/vulkan/tests/block_pool_no_free.c - mesa/src/intel/vulkan/tests/state_pool_free_list_only.c This is obviously because gen_clflush.h contains code that uses intrinsics that are only available with SSE3. Since the driver already uses SSE3, it seems reasonable to add this to the tests as well. Signed-off-by: Erik Faye-Lund <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Eric Engeström <[email protected]>
* intel/aub_viewer: highlight true booleansLionel Landwerlin2018-12-283-2/+10
| | | | | | | Useful to spot PIPE_CONTROL flags. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* intel/aub_viewer: fold binding/sampler table itemsLionel Landwerlin2018-12-281-4/+11
| | | | | | | Makes things easier to read rather than a long block of text. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* intel/aub_viewer: fix shader viewLionel Landwerlin2018-12-281-1/+3
| | | | | | | Not decoding the shader at the right offset. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* intel/aub_viewer: print address of missing shaderLionel Landwerlin2018-12-281-1/+2
| | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* intel/aub_viewer: fixup 0x address prefixLionel Landwerlin2018-12-281-1/+1
| | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* intel/aub_viewer: fix shader get_boLionel Landwerlin2018-12-281-6/+2
| | | | | | | Instruction addresses are always in ppgtt space. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* anv: don't do partial resolve on layer > 0Lionel Landwerlin2018-12-241-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | We've made the choice not to use fast clears on layer > 0 with multilayer images. This is partly because we would need to store multiple clear colors for each layer, making the existing memory layout, already including aux surfaces, fast clear color, image state, etc... even more complex. Partial resolves are the operations transfering the clear colors into the auxiliary buffers. This operation is currently implemented in Blorp by loading the clear color from the image's BO, into a shader that then samples from the auxiliary buffer and writes the color only if it isn't there already. The problem here is that because we store only one clear color for all layers and it is used for partial resolves. If you trigger a partial clear on a layer > 0, then you're likely to deal with a color that is not what you actually want. In the particular issues below, we have multiple layers, each cleared with a different color but the partial resolve just writes the wrong color into the auxiliary buffers for layers > 0. Signed-off-by: Lionel Landwerlin <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108910 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108911 Cc: [email protected]
* intel/compiler: move nir_lower_bool_to_int32 before nir_lower_locals_to_regsIago Toral Quiroga2018-12-201-2/+2
| | | | | | | | | | | | The former expects to see SSA-only things, but the latter injects registers. The assertions in the lowering where not seeing this because they asserted on the bit_size values only, not on the is_ssa field, so add that assertion too. Fixes: 11dc1307794e "nir: Add a bool to int32 lowering pass" CC: [email protected] Reviewed-by: Jason Ekstrand <[email protected]>
* anv/android: turn on VK_ANDROID_external_memory_android_hardware_bufferTapani Pälli2018-12-191-0/+1
| | | | | Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* anv: ignore VkSamplerYcbcrConversion on non-yuv formatsTapani Pälli2018-12-191-1/+6
| | | | | | | | | | | | | | | | | This fulfills a requirement for clients that want to utilize same code path for images with external formats (VK_FORMAT_UNDEFINED) and "regular" RGBA images where format is known. This is similar to how OES_EGL_image_external works. To support this, we allow color conversion samplers for non-YUV formats but skip setting up conversion when format does not have can_ycbcr flag set. v2: add comment and bundle can_ycbcr to the existing break condition (Lionel) Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* anv: support VkSamplerYcbcrConversionInfo in vkCreateImageViewTapani Pälli2018-12-191-1/+26
| | | | | | | | | | | If a conversion struct was passed, then initialize view using format from the conversion structure. v2: use vk_format directly from the anv_format struct v3: added some assertions (Lionel) Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* anv: add VkFormat field as part of anv_formatTapani Pälli2018-12-192-0/+5
| | | | | Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
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