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* intel/vec4: fix valgrind errors with vf_values arrayTapani Pälli2020-02-071-1/+2
| | | | | | | | | | | Fixes valgrind errors introduced since commit a8ec4082. Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2346 Fixes: a8ec4082 ("nir+vtn: vec8+vec16 support") Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Matt Turner <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3691> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3691>
* anv: No-op submit and wait calls when no_hw is setJason Ekstrand2020-02-061-0/+12
| | | | | | Reviewed-by: Lionel Landwerlin <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3734> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3734>
* anv: set MOCS on push constantsLionel Landwerlin2020-02-061-1/+7
| | | | | | | | | | v2: Also set MOCS on 3DSTATE_CONSTANT_ALL (Ken) Signed-off-by: Lionel Landwerlin <[email protected]> Fixes: 67d2cb3e9367 ("anv: Add get_push_range_address() helper.") Reviewed-by: Jason Ekstrand <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3732> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3732>
* intel: Load the driver even if I915_PARAM_REVISION is not found.Rafael Antognolli2020-02-061-1/+1
| | | | | | | | | | | | | | | This param is only available starting on kernel 4.1. Use a default value of 0 if it is not found instead. v2: Update commit message (Lionel) Cc: Jordan Justen <[email protected]> Cc: Mark Janes <[email protected]> Fixes: 96e1c945f2b ("i965: Move device info initialization to common Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kristian H. Kristensen <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3727> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3727>
* isl: Fix the android build.Kenneth Graunke2020-02-051-1/+2
| | | | | | Fixes: 5bea0cf7795 ("intel/isl: Move iris's pipe-to-isl format function to isl.") Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3729> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3729>
* intel/genxml: Drop "reserved" enumKenneth Graunke2020-02-051-1/+0
| | | | | | | | | | | This was adding "#define reserved 2" to genxml includes, which is a fairly mean lowercase word to redefine. It ends up breaking the build on Android, which has __u32 reserved fields in headers. Defining it also has no purpose. Just drop it. Fixes: 5bea0cf7795 ("intel/isl: Move iris's pipe-to-isl format function to isl.") Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3729>
* glsl,nir: Switch the enum representing shader image formats to PIPE_FORMAT.Eric Anholt2020-02-051-57/+3
| | | | | | | | | | | | | | | | | This means you can directly use format utils on it without having to have your own GL enum to number-of-components switch statement (or whatever) in your vulkan backend. Thanks to imirkin for fixing up the nouveau driver (and a couple of core details). This fixes the computed qualifiers for EXT_shader_image_load_store's non-integer sizeNxM qualifiers, which we don't have tests for. Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> (v3d) Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3355> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3355>
* intel/isl: Move iris's pipe-to-isl format function to isl.Eric Anholt2020-02-052-0/+302
| | | | | | | | | | This will get reused in the shader compiler once we switch it over to pipe formats instead of GL enums. We can't easily deduplicate i965's mesa-to-isl mapping because of cases like A32_FLOAT that are mapped differently. Reviewed-by: Jason Ekstrand <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3355>
* intel/fs: Don't count integer instructions as being possibly coissueIan Romanick2020-02-051-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Integer instructions don't coissue. Before e64be391dd0 ("intel/compiler: generalize the combine constants pass"), this pass only looked at float sources. There's no shader-db data in that commit, so I collected some. The results are not good: Haswell total instructions in shared programs: 11898805 -> 11908127 (0.08%) instructions in affected programs: 1218680 -> 1228002 (0.76%) helped: 2 HURT: 5171 helped stats (abs) min: 12 max: 111 x̄: 61.50 x̃: 61 helped stats (rel) min: 1.59% max: 9.20% x̄: 5.40% x̃: 5.40% HURT stats (abs) min: 1 max: 311 x̄: 1.83 x̃: 1 HURT stats (rel) min: 0.02% max: 9.91% x̄: 1.05% x̃: 0.70% 95% mean confidence interval for instructions value: 1.55 2.05 95% mean confidence interval for instructions %-change: 1.02% 1.08% Instructions are HURT. total cycles in shared programs: 221664974 -> 221404750 (-0.12%) cycles in affected programs: 120012620 -> 119752396 (-0.22%) helped: 3464 HURT: 3159 helped stats (abs) min: 1 max: 428160 x̄: 314.55 x̃: 16 helped stats (rel) min: <.01% max: 57.33% x̄: 3.40% x̃: 1.28% HURT stats (abs) min: 1 max: 87846 x̄: 262.54 x̃: 14 HURT stats (rel) min: <.01% max: 85.57% x̄: 3.01% x̃: 0.77% 95% mean confidence interval for cycles value: -224.23 145.65 95% mean confidence interval for cycles %-change: -0.50% -0.19% Inconclusive result (value mean confidence interval includes 0). total spills in shared programs: 9804 -> 10047 (2.48%) spills in affected programs: 6869 -> 7112 (3.54%) helped: 2 HURT: 41 total fills in shared programs: 19863 -> 20319 (2.30%) fills in affected programs: 17428 -> 17884 (2.62%) helped: 2 HURT: 41 LOST: 20 GAINED: 13 This also prevents regressions in "intel/fs: Promote integer constants after lowering integer multiplication" (note: that patch will probably not be committed). When the passes are reorderd, code like mul(8) acc0<1>D g9<8,8,1>D -2078209981D { align1 1Q }; gets turned into mov(1) g23<1>D 2078209981D { align1 WE_all 1N }; ... mul(8) acc0<1>D g13<8,8,1>D -g23<0,1,0>D { align1 1Q compacted }; It's not 100% clear why, but these produce different results. Note that -2078209981 & 0x0ffff = 0x0843, and -(2078209981 & 0x0ffff) = 0xffff0843. It seems like the upper 16-bits of the negation should be ignored. Fixes: e64be391dd0 ("intel/compiler: generalize the combine constants pass") Cc: Iago Toral Quiroga <[email protected]> Suggested-by: Matt Turner <[email protected]> Reviewed-by: Matt Turner <[email protected]> The shaders with spills or fills hurt are the usual suspects. A couple compute shaders in Dirt Showdown and a compute shader in Bioshock Infinite. On Haswell, a compute shader (that appears twice in shader-db) from Aztec Ruins was also hurt for spill and fills. Haswell total instructions in shared programs: 11573934 -> 11568335 (-0.05%) instructions in affected programs: 828623 -> 823024 (-0.68%) helped: 2825 HURT: 6 helped stats (abs) min: 1 max: 134 x̄: 2.16 x̃: 1 helped stats (rel) min: 0.02% max: 9.05% x̄: 0.84% x̃: 0.61% HURT stats (abs) min: 1 max: 216 x̄: 81.83 x̃: 56 HURT stats (rel) min: 0.16% max: 8.65% x̄: 4.21% x̃: 4.68% 95% mean confidence interval for instructions value: -2.31 -1.64 95% mean confidence interval for instructions %-change: -0.85% -0.80% Instructions are helped. total cycles in shared programs: 187573593 -> 187004633 (-0.30%) cycles in affected programs: 82816107 -> 82247147 (-0.69%) helped: 2186 HURT: 1741 helped stats (abs) min: 1 max: 35230 x̄: 326.96 x̃: 16 helped stats (rel) min: <.01% max: 46.11% x̄: 3.11% x̃: 0.90% HURT stats (abs) min: 1 max: 6138 x̄: 83.73 x̃: 16 HURT stats (rel) min: <.01% max: 104.11% x̄: 2.73% x̃: 0.75% 95% mean confidence interval for cycles value: -197.13 -92.64 95% mean confidence interval for cycles %-change: -0.72% -0.33% Cycles are helped. total spills in shared programs: 7870 -> 7743 (-1.61%) spills in affected programs: 2260 -> 2133 (-5.62%) helped: 31 HURT: 5 total fills in shared programs: 6320 -> 6263 (-0.90%) fills in affected programs: 3547 -> 3490 (-1.61%) helped: 31 HURT: 6 LOST: 9 GAINED: 9 Ivybridge total instructions in shared programs: 11863372 -> 11859793 (-0.03%) instructions in affected programs: 757183 -> 753604 (-0.47%) helped: 2236 HURT: 3 helped stats (abs) min: 1 max: 81 x̄: 1.86 x̃: 1 helped stats (rel) min: 0.03% max: 5.26% x̄: 0.74% x̃: 0.48% HURT stats (abs) min: 11 max: 301 x̄: 192.33 x̃: 265 HURT stats (rel) min: 1.55% max: 10.51% x̄: 6.89% x̃: 8.62% 95% mean confidence interval for instructions value: -2.01 -1.18 95% mean confidence interval for instructions %-change: -0.77% -0.70% Instructions are helped. total cycles in shared programs: 178377378 -> 177946087 (-0.24%) cycles in affected programs: 76261390 -> 75830099 (-0.57%) helped: 1635 HURT: 1395 helped stats (abs) min: 1 max: 34796 x̄: 333.53 x̃: 16 helped stats (rel) min: <.01% max: 47.15% x̄: 2.82% x̃: 0.64% HURT stats (abs) min: 1 max: 4315 x̄: 81.74 x̃: 18 HURT stats (rel) min: <.01% max: 49.98% x̄: 1.99% x̃: 0.53% 95% mean confidence interval for cycles value: -197.06 -87.62 95% mean confidence interval for cycles %-change: -0.78% -0.43% Cycles are helped. total spills in shared programs: 4188 -> 4182 (-0.14%) spills in affected programs: 1557 -> 1551 (-0.39%) helped: 30 HURT: 3 total fills in shared programs: 5056 -> 5245 (3.74%) fills in affected programs: 2708 -> 2897 (6.98%) helped: 30 HURT: 3 LOST: 5 GAINED: 1 No shader-db changes on any other Intel platform. Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3544> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3544>
* anv: implement gen12 post sync pipe control workaroundLionel Landwerlin2020-02-051-1/+5
| | | | | | | | | | | Same as Skylake. v2: Restrict to A0 Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3405> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3405>
* anv: implement gen9 post sync pipe control workaroundLionel Landwerlin2020-02-053-0/+39
| | | | | | | | | | | | | | We've been missing this workaround for a while and since it's required for Gen12, let's implement it for Gen9 first. v2: Update comment for Gen9. v3: Fix clearing of bits... (Lionel) Signed-off-by: Lionel Landwerlin <[email protected]> Cc: <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3405>
* anv/blorp: Use the correct size for vkCmdCopyBufferToImageJason Ekstrand2020-02-021-0/+8
| | | | | | | | | | | | | Now that we're using an uncompressed format for the buffer, we have to scale down the dimensions we pass into BLORP when doing buffer->image copies. Fixes: dd92179a72 "anv: Canonicalize buffer formats for image/buffer..." Closes: #2452 Reviewed-by: Erik Faye-Lund <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3664> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3664>
* intel/gen12+: Set way_size_per_bank to 4Anuj Phogat2020-01-311-1/+1
| | | | | | | | This patch fixes the way_size_per_bank for Gen12+ Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Sagar Ghuge<[email protected]>
* intel/gen12+: Reserve 4KB of URB space per bank for Compute EngineAnuj Phogat2020-01-311-1/+19
| | | | | | | | | | | | This patch is required to fix 11K+ vulkan CTS failures we were getting with way_size_per_bank of 4 (see next patch). Thanks to Sagar Ghuge and Jordan Justen for all the hard work of debugging and testing. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Sagar Ghuge<[email protected]>
* intel/fs: Write the address register with NoMask for MOV_INDIRECTJason Ekstrand2020-01-311-0/+9
| | | | | | | | | | | This fixes a hang in the following Vulkan CTS test on TGL-LP: dEQP-VK.descriptor_indexing.storage_buffer_dynamic_in_loop Cc: [email protected] Reviewed-by: Kenneth Graunke <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3642> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3642>
* intel/tools: Handle strides better when dumping buffersJason Ekstrand2020-01-311-2/+5
| | | | | | | | | | | The old code would only break at stride boundaries if the stride was less than 32B; otherwise it would just break every 32B. This commit makes it break at stride boundaries and 32B boundaries (starting from the last stride). This makes reading large vertex buffers in aubinator much nicer. Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3642>
* intel/disasm: SEND has two sources on Gen12+Jason Ekstrand2020-01-311-2/+4
| | | | | | Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3642>
* intel/eu/validate: Don't validate regions of sendsJason Ekstrand2020-01-311-3/+3
| | | | | | | | | | Otherwise, the validator tries to read the type of src1 of a SEND/SENDS which doesn't actually have a type field. This prevents validation issues in the next commit. Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3642>
* anv: Always fill out the AUX table even if CCS is disabledJason Ekstrand2020-01-303-16/+18
| | | | | | | Cc: "20.0" [email protected] Reviewed-by: Kenneth Graunke <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3454> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3454>
* anv: Plumb deref block size through to 3DSTATE_SFJason Ekstrand2020-01-304-11/+18
| | | | | | Cc: "20.0" [email protected] Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3454>
* intel/blorp: Plumb deref block size through to 3DSTATE_SFJason Ekstrand2020-01-301-6/+10
| | | | | | Cc: "20.0" [email protected] Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3454>
* intel/common: Return the block size from get_urb_configJason Ekstrand2020-01-304-4/+51
| | | | | | Cc: "20.0" [email protected] Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3454>
* anv: Emit URB setup earlierJason Ekstrand2020-01-301-2/+2
| | | | | | Cc: "20.0" [email protected] Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3454>
* intel/blorp: Always emit URB config on Gen7+Jason Ekstrand2020-01-302-20/+46
| | | | | | | | | | | | | | | Previously, i965/iris tried to reuse the currently programmed URB config if it was good enough for BLORP, rather than reprogramming it each time. However, this will make some things harder on Gen12+ and we've not seen any performance impact from emitting URB more frequently in ANV. This makes the blorp <-> driver interface a bit simpler on Gen7+ because now all the driver has to do is to provide the L3$ config rather than trying to hand off URB re-config to blorp. Cc: "20.0" [email protected] Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3454>
* intel: Take a gen_l3_config in gen_get_urb_configJason Ekstrand2020-01-303-15/+11
| | | | | | | | | | Instead of making each driver pass in the same push constant size and do it's own L3$ config URB size calculation, just make them pass in their L3$ configuration. Cc: "20.0" [email protected] Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3454>
* intel/genxml: Drop SLMEnable from L3CNTLREG on Gen11Jason Ekstrand2020-01-302-2/+1
| | | | | | | | | | | | SML is no longer in the L3$ on Gen11+. It's not incredibly clear from the docs but no Gen11 platforms are in the list of platforms on which this bit exists. Also, we've been always setting it false on Gen11 in ANV and i965 thanks to GEN_L3P_SLM being zero with no ill effects. Cc: "20.0" [email protected] Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3454>
* anv,iris: Set 3DSTATE_SF::DerefBlockSize to per-poly on Gen12+Jason Ekstrand2020-01-302-1/+9
| | | | | | | | | | | According to the BSpec, this should prevent hangs when using shaders with large URB entries. A more precise fix can be done but it requires re-arranging URB setup. Cc: [email protected] Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3454>
* genxml: Add a new 3DSTATE_SF field on gen12Jason Ekstrand2020-01-301-0/+5
| | | | | | | Cc: [email protected] Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3454>
* anv: Rename a variableJason Ekstrand2020-01-291-2/+2
| | | | | The name "desc" shadows another variable. Name it "desc_data" like all of the other descriptor data variables in this file.
* anv/block_pool: Ensure allocations have contiguous mapsJason Ekstrand2020-01-295-15/+32
| | | | | | | | | | | | | | | | | | | | | | Because softpin block pools are made up of a set of BOs with different maps, it was possible for a single state to end up straddling blocks. To fix this, we pass a contiguous size to anv_block_pool_grow and it ensures that the next allocation in the pool will have at least that size. We also add an assert in anv_block_pool_map to ensure we always get contiguous maps. Prior to the changes to anv_block_pool_grow, the unit tests failed with this assert. With this patch, the tests pass. This was causing problems on Gen12 where we allocate the pages for the AUX table from the dynamic state pool. The first chunk, which gets allocated very early in the pool's history, is 1MB which was enough that it was getting multiple BOs. This caused the gen_aux_map code to write outside of the map and overwrite the instruction state pool buffer which lead to GPU hangs. Fixes: 731c4adcf9b "anv/allocator: Add support for non-userptr" Reviewed-by: Lionel Landwerlin <[email protected]>
* anv: Re-use one old BT block in reset_batch_bo_chainJason Ekstrand2020-01-291-1/+2
| | | | | | | | | We intentionally throw away all but one BT block but then we set cmd_buffer->bt_block to ANV_STATE_NULL instead of the one we hung on to. This causes the command buffer to immediately re-emit STATE_BASE_ADDRESS the first time a BT is needed for no good reason. Reviewed-by: Lionel Landwerlin <[email protected]>
* anv: Set actual state pool sizes when we have softpinJason Ekstrand2020-01-291-5/+13
| | | | Reviewed-by: Lionel Landwerlin <[email protected]>
* anv: Emit CS Stall before Instruction Cache flush for gen12 WAJordan Justen2020-01-281-0/+6
| | | | | | | | | | | | | Before flushing the instruction cache with a pipe control, we need to use a CS Stall pipe control. Ref: GEN:BUG:1409226450 Rework: Add stall-at-scoreboard (Lionel) Rework: Merge with other anvil pre-invalidate stalls (Lionel) Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3457> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3457>
* intel/mi_builder: Force write completion on Gen12+Jason Ekstrand2020-01-281-0/+3
| | | | | | | | | | | Otherwise, we have no guarantee that the write actually lands before we move on to other things. Doing this on every SDI is probably a bit harsh but it's safe. We should figure out a good way to avoid this when we can. Reviewed-by: Lionel Landwerlin <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3593> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3593>
* anv: Replace one more aux_surface.isl.size_B checkJason Ekstrand2020-01-281-1/+1
| | | | | | | | This one was missed in 41bffe09135. Fixes: 41bffe09135 "anv: Replace aux_surface.isl.size_B checks with..." Reviewed-by: Lionel Landwerlin <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3593>
* intel/blorp: Handle bit-casting UNORM and BGRA formatsJason Ekstrand2020-01-281-37/+34
| | | | | | | | | | | | In f132e0fddfa, I attempted to allow BLORP to do CCS_E copies by using the UNORM formats instead. However, the old BLORP bit-cast code could only handle RGBA formats and asserted on anything other than UINT formats. The reason we didn't catch this is because it only comes up on Gen12 platforms which aren't in our normal CI yet. Fixes: f132e0fddfad "intel/blorp: Add support for CCS_E copies with..." Reviewed-by: Lionel Landwerlin <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3593>
* anv: Handle unavailable queries in vkCmdCopyQueryPoolResultsBrian Ho2020-01-281-0/+54
| | | | | | | | | | | | | | | If VK_QUERY_RESULT_WAIT_BIT is not set, there is currently no special handling of unavailable queries in vkCmdCopyQueryPoolResults, and anv will write an invalid value for the query result. This commit updates vkCmdCopyQueryPoolResults for unavailable queries to return 0 if the VK_QUERY_RESULT_PARTIAL_BIT flag is set and if not, skip writing altogether. Cc: <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3586> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3586>
* anv: Properly fetch partial results in vkGetQueryPoolResultsBrian Ho2020-01-281-2/+11
| | | | | | | | | | | | | | | | | Currently, fetching the partial results (VK_QUERY_RESULT_PARTIAL_BIT) of an unavailable occlusion query via vkGetQueryPoolResults can return invalid values. anv returns slot.end - slot.begin, but in the case of unavailable queries, slot.end is still at the initial value of 0. If slot.begin is non-zero, the occlusion count underflows to a value that is likely outside the acceptable range of the partial result. This commit fixes vkGetQueryPoolResults by always returning 0 if the query is unavailable and the VK_QUERY_RESULT_PARTIAL_BIT is set. Cc: <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3586>
* anv/android: make format_supported_with_usage staticTapani Pälli2020-01-281-1/+1
| | | | | | | | Signed-off-by: Tapani Pälli <[email protected]> Acked-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kristian H. Kristensen <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3532> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3532>
* anv/android: setup gralloc1 usage from gralloc0 usage manuallyTapani Pälli2020-01-282-8/+17
| | | | | | | | | This cuts away dependency to libgrallocusage. Signed-off-by: Tapani Pälli <[email protected]> Acked-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kristian H. Kristensen <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3532>
* anv: Insert holes for non-existant XFB varyingsJason Ekstrand2020-01-271-5/+17
| | | | | | | | | | | Thanks to optimizations, it's possible for varyings to get deleted but still leave the variable there for nir_gather_xfb_info to find. If we get into this case, insert a hole. Fixes: 36ee2fd61c8 "anv: Implement the basic form of..." Reviewed-by: Lionel Landwerlin <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3520> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3520>
* intel/genxml: Make SO_DECL::"Hole Flag" a BooleanJason Ekstrand2020-01-277-7/+7
| | | | | Reviewed-by: Lionel Landwerlin <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3520>
* intel/compiler: Clear accumulator register before EOTSagar Ghuge2020-01-271-0/+18
| | | | | | | | | | | | | | | | | | | | | | | v2: (Francisco Jerez) - Drop vec4 changes. - Handle explicit acc0 operand and implicit one. - Make sure instruction is SIMD16, prediction is off and default mask control set to true. v3: (Francisco Jerez) - Clear accumulator only when it's written. - Use BRW_MASK_DISABLE instead of true. - Use correct width for brw_acc_reg(). - Fix last_inst_offset. v4: (Francisco Jerez) - Don't check for last instruction for accummulator write. Signed-off-by: Sagar Ghuge <[email protected]> Reviewed-by: Francisco Jerez <[email protected]> Reviewed-by: Matt Turner <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3376> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3376>
* isl: add gen12 comment about CCS for linear tilingLionel Landwerlin2020-01-261-0/+10
| | | | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3551> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3551>
* isl: drop CCS row pitch requirement for linear surfacesLionel Landwerlin2020-01-261-15/+21
| | | | | | | | | | | | | | | | | | | | | | | | We were applying row pitch constraint of CCS surfaces to linear surfaces. But CCS is only supported in linear tiling under some condition (more on that in the following commit). So let's drop that requirement for now. Fixes a bunch of crucible assert where the byte size of a linear image is expected to be similar to the byte size of buffer for the same extent in the following category : func.miptree.r8g8b8a8-unorm.aspect-color.view-2d.*download-copy-with-draw.* v2: Move restriction to isl_calc_tiled_min_row_pitch() v3: Move restrinction to isl_calc_row_pitch_alignment() (Jason) v4: Update message (Lionel) Signed-off-by: Lionel Landwerlin <[email protected]> Fixes: 07e16221d975 ("isl: Round up some pitches to 512B for Gen12's CCS") Reviewed-by: Jason Ekstrand <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3551>
* intel: Implement Gen12 workaround for array textures of size 1Lionel Landwerlin2020-01-266-1/+151
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Gen12 does not support RENDER_SURFACE_STATE::SurfaceArray = true && RENDER_SURFACE_STATE::Depth = 0. SurfaceArray can only be set to true if Depth >= 1. We workaround this limitation by adding the max(value, 1) snippet in the shaders on the 3 components for texture array sizes. Tested on Gen9 with the following Vulkan CTS tests : dEQP-VK.image.image_size.2d_array.* v2: Drop debug print (Tapani) Switch to GEN:BUG instead of Wa_ v3: Fix dEQP-VK.image.image_size.1d_array.* cases (Lionel) v4: Fix dEQP-VK.glsl.texture_functions.query.texturesize.* cases (Missing tex_op handling) (Lionel) v5: Missing break statement (Lionel) v6: Fixup comment (Tapani) v7: Fixup comment again (Tapani) v8: Don't use sample_dim as index (Jason) Rename pass Simplify control flow Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Tapani Pälli <[email protected]> (v7) Reviewed-by: Jason Ekstrand <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3362> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3362>
* intel/isl: Allow CCS_E on more formatsJason Ekstrand2020-01-251-23/+4
| | | | | | | | | Now that BLORP supports copies on everything except R11G11B10_FLOAT, we should be able to support CCS_E those formats. Reviewed-by: Kenneth Graunke <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3554> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3554>
* intel/blorp: Add support for CCS_E copies with UNORM formatsJason Ekstrand2020-01-251-7/+38
| | | | | | | | | | Some of the smaller bit-size formats which support CCS_E don't have a UINT representative in their compression class. However, we should be able to use UNORM just fine and still get bit-exact copies. We just have to do a conversion to/from UNORM when we bitcast. Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3554>
* anv: Rework CCS memory handling on TGL-LPJason Ekstrand2020-01-256-70/+232
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The previous way we were attempting to handle AUX tables on TGL-LP was very GL-like. We used the same aux table management code that's shared with iris and we updated the table on image create/destroy. The problem with this is that Vulkan allows multiple VkImage objects to be bound to the same memory location simultaneously and the app can ping-pong back and forth between them in the same command buffer. Because the AUX table contains format-specific data, we cannot support this ping-pong behavior with only CPU updates of the AUX table. The new mechanism switches things around a bit and instead makes the aux data part of the BO. At BO creation time, a bit of space is appended to the end of the BO for AUX data and the AUX table is updated in bulk for the entire BO. The problem here, of course, is that we can't insert the format-specific data into the AUX table at BO create time. Fortunately, Vulkan has a requirement that every TILING_OPTIMAL image must be initialized prior to use by transitioning the image from VK_IMAGE_LAYOUT_UNDEFINED to something else. When doing the above described ping-pong behavior, the app has to do such an initialization transition every time it corrupts the underlying memory of the VkImage by using it as something else. We can hook into this initialization and use it to update the AUX-TT entries from the command streamer. This way the AUX table gets its format information, apps get aliasing support, and everyone is happy. One side-effect of this is that we disallow CCS on shared buffers. We'll need to fix this for modifiers on the scanout path but that's a task for another patch. We should be able to do it with dedicated allocations. Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3519> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3519>
* anv: Make anv_vma_alloc/free a lot dumberJason Ekstrand2020-01-253-69/+80
| | | | | | | | | | | | All they do now is take a size, align, and flags and figure out which heap to allocate in. All of the actual code to deal with the BO is in anv_allocator.c. We want to leave anv_vma_alloc/free in anv_device.c because it deals with API-exposed heaps so it still makes sense to have it there. Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3519>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-14 16:47:01 +0000