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* intel/perf: add TGL supportLionel Landwerlin2019-10-314-0/+8611
* intel/compiler: Report the number of non-spill/fill SEND messages on vec4 tooIan Romanick2019-10-301-5/+35
* intel/dev: set default num_eu_per_subslice on gen12Lionel Landwerlin2019-10-301-1/+2
* intel/eu/validate/gen12: Add TGL to eu_validate tests.Jordan Justen2019-10-301-0/+9
* intel/dev: Add preliminary device info for TigerlakeJordan Justen2019-10-301-0/+49
* intel/dump_gpu: handle context create extended ioctlLionel Landwerlin2019-10-301-0/+15
* anv: Add Tile Cache Flush for Unified Cache.Rafael Antognolli2019-10-303-1/+45
* blorp: Add Tile Cache Flush for Unified Cache.Rafael Antognolli2019-10-301-0/+3
* intel/genxml: Add gen12 tile cache flush bitJordan Justen2019-10-301-0/+1
* anv: Align fast clear color state buffer to a page.Rafael Antognolli2019-10-301-0/+9
* intel/compiler: Add instruction compaction support on Gen12Matt Turner2019-10-302-184/+868
* intel/compiler: Make separate src0/src1 index tablesMatt Turner2019-10-301-11/+18
* intel/compiler: Inline get_src_index()Matt Turner2019-10-301-26/+15
* intel/compiler: Restructure instruction compaction in preparation for Gen12Matt Turner2019-10-301-20/+28
* intel/compiler: Remove unreachable() from brw_reg_type.cMatt Turner2019-10-301-3/+3
* anv: Avoid emitting UBO surface states that won't be usedJason Ekstrand2019-10-301-1/+12
* intel/vec4: Set brw_stage_prog_data::has_ubo_pullJason Ekstrand2019-10-301-0/+2
* intel/isl: Allow stencil buffer to support compression on Gen12+Sagar Ghuge2019-10-291-2/+3
* intel/blorp: Set stencil resolve enable bitSagar Ghuge2019-10-291-4/+17
* intel: Track stencil aux usage on Gen12+Sagar Ghuge2019-10-293-0/+9
* intel/blorp: Add helper function for stencil buffer resolveSagar Ghuge2019-10-292-0/+34
* intel/blorp: Assign correct view while clearing depth stencilSagar Ghuge2019-10-291-1/+1
* genxml/gen12: Add Stencil Buffer Resolve Enable bitSagar Ghuge2019-10-291-0/+1
* anv: Reduce the minimum number of relocationsJason Ekstrand2019-10-291-1/+1
* anv: Delay allocation of relocation listsJason Ekstrand2019-10-291-67/+71
* anv: Implement new way for setting streamout buffers.Plamena Manolova2019-10-293-0/+19
* genxml: Add 3DSTATE_SO_BUFFER_INDEX_* instructionsPlamena Manolova2019-10-291-0/+47
* anv: Set depthBounds to true in anv_GetPhysicalDeviceFeatures.Plamena Manolova2019-10-291-1/+1
* genxml: Change 3DSTATE_DEPTH_BOUNDS bias.Plamena Manolova2019-10-291-1/+1
* intel/perf: update ICL configurationsLionel Landwerlin2019-10-291-59/+28
* anv: Fix output of INTEL_DEBUG=bat for chained batchesCaio Marcelo de Oliveira Filho2019-10-281-1/+1
* loader: default to iris for all future PCI IDsEric Engestrom2019-10-282-0/+3
* anv: add a couple printflike() annotationsEric Engestrom2019-10-281-2/+4
* intel/isl: Support lossless compression with multisamplesSagar Ghuge2019-10-281-5/+1
* intel/blorp: Use isl_aux_usage_has_mcs instead of comparingSagar Ghuge2019-10-281-5/+7
* intel/isl: Don't reconfigure aux surfaces for MCSSagar Ghuge2019-10-281-0/+3
* intel/blorp: Satisfy clear color rules for HIZ_CCSNanley Chery2019-10-281-1/+35
* intel: Fix and use HIZ_CCS write through modeNanley Chery2019-10-282-0/+7
* intel/blorp: Satisfy HIZ_CCS fast-clear alignmentsNanley Chery2019-10-281-0/+47
* intel: Refactor blorp_can_hiz_clear_depth()Nanley Chery2019-10-283-16/+19
* isl: Add isl_surf_supports_hiz_ccs_wt()Nanley Chery2019-10-282-0/+18
* intel/blorp: Treat HIZ_CCS like HiZNanley Chery2019-10-281-2/+2
* intel/blorp: Assert against HiZ in surface statesNanley Chery2019-10-281-2/+1
* intel: Support HIZ_CCS in isl_surf_get_ccs_surfNanley Chery2019-10-283-7/+38
* isl: Reduce assertions during aux surf creationNanley Chery2019-10-281-5/+15
* intel: Enable CCS_E for R24_UNORM_X8_TYPELESS on TGL+Nanley Chery2019-10-282-1/+2
* intel: Use 3DSTATE_DEPTH_BUFFER::ControlSurfaceEnableNanley Chery2019-10-282-1/+2
* intel/isl: Support HIZ_CCS in emit_depth_stencil_hizJason Ekstrand2019-10-281-2/+10
* intel: Use RENDER_SURFACE_STATE::DepthStencilResourceNanley Chery2019-10-282-0/+6
* intel: Update alignment restrictions for HiZ surfaces.Jordan Justen2019-10-281-1/+7
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