summaryrefslogtreecommitdiffstats
path: root/src/intel
Commit message (Collapse)AuthorAgeFilesLines
* anv: Take a single aspect in anv_layout_to_aux_usageJason Ekstrand2017-10-063-18/+15
| | | | Reviewed-by: Lionel Landwerlin <[email protected]>
* anv/cmd_buffer: Make get_fast_clear_state return an addressJason Ekstrand2017-10-061-22/+24
| | | | Reviewed-by: Lionel Landwerlin <[email protected]>
* anv/blorp: Add a concept of default aux usageJason Ekstrand2017-10-061-11/+16
| | | | | | | A good chunk of anv_blorp just wants the aux usage from the image. This magic aux_usage value means just that. Reviewed-by: Lionel Landwerlin <[email protected]>
* anv: add nir lowering pass for ycbcr texturesLionel Landwerlin2017-10-066-2/+496
| | | | | | | | | | | | | | | | | | This pass implements all the implicit conversions required by the VK_KHR_sampler_ycbcr_conversion specification. It also inserts plane sources onto sampling instructions that we then let the pipeline layout pass deal with, when mapping things correctly to descriptors. v2: Add new file to meson build (Lionel) Use nir_frcp() rather than (1.0f / x) (Jason) Reuse nir_tex_instr_dest_size() rather than handwritten one (Jason) Return progress (Jason) Account for array of samplers (Jason) Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* anv: prepare sampler emission code for multiplanar imagesLionel Landwerlin2017-10-063-41/+43
| | | | | | | | | | New settings from the KHR_sampler_ycbcr_conversion specifications might require different sampler settings for luma and chroma planes. This change makes the sampler table emission ready to handle multiple planes. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* anv/apply_pipeline_layout: Prepare for multi-planar imagesLionel Landwerlin2017-10-064-22/+116
| | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* anv: add new formats KHR_sampler_ycbcr_conversionLionel Landwerlin2017-10-063-6/+189
| | | | | | | Adding new downsampling factors for each planes. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* anv: modify the internal concept of format to express multiple planesLionel Landwerlin2017-10-064-256/+331
| | | | | | | | | | | | | | | A given Vulkan format can now be decomposed into a set of planes. We now use 'struct anv_format_plane' to represent the format of those planes. v2: by Jason Rename anv_get_plane_format() to anv_get_format_plane() Don't rename anv_get_isl_format() Replace ds_fmt() by fmt2() Introduce fmt_unsupported() Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* anv: prepare formats to handle disjoints setsLionel Landwerlin2017-10-061-10/+27
| | | | | | | | | | | Newer format enums start at offset 1000000000, making it impossible to have them all in one table. This change splits the formats into sets that we then access through indirection. v2: rename format_extract to vk_to_anv_format (Chad/Jason) Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* isl: fill out layout descriptions for yuv formatsLionel Landwerlin2017-10-061-4/+4
| | | | | | | Some description was missing. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* isl: check whether a format is rgb if colorspace is yuvLionel Landwerlin2017-10-061-0/+2
| | | | | | | Suggested by Chad. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* isl: make format layout channels accessible by indexLionel Landwerlin2017-10-061-9/+12
| | | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Chad Versace <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/compiler: Don't propagate cmod into integer multipliesJason Ekstrand2017-10-052-0/+34
| | | | | | | No shader-db change on Sky Lake. Reviewed-by: Matt Turner <[email protected]> Cc: [email protected]
* intel/compiler: Don't cmod propagate into a saturated operationJason Ekstrand2017-10-052-0/+16
| | | | | | | | | | | | Shader-db results on Sky Lake: total instructions in shared programs: 12954445 -> 12955125 (0.01%) instructions in affected programs: 141862 -> 142542 (0.48%) helped: 0 HURT: 626 Reviewed-by: Matt Turner <[email protected]> Cc: [email protected]
* i965: Validate "Special Requirements for Handling Double Precision Data Types"Matt Turner2017-10-042-0/+792
| | | | | | | | | | | | | I did not implement: CNL's restriction on 64-bit int + align16, because I don't think we'll ever use this combination regardless of hardware generation. The restriction on immediate DF -> F conversions, because there's no reason to ever generate that, and I don't even know how DF -> F conversions are supposed to work in Align16 since (1) the dst stride must be 1, but (2) the dst stride would have to be 2 for src and dst strides to be aligned.
* i965: Fix and enable forgotten validation testMatt Turner2017-10-041-14/+17
| | | | I seem to have forgotten I still had work to do.
* i965: Only insert error message if not already presentMatt Turner2017-10-041-5/+13
| | | | | | | Some restrictions require something like strides to match between src and dest. For multi-source instructions, I'd rather encapsulate the logic for not inserting already present errors in ERROR_IF than open-coding it multiple places.
* i965: Avoid validation error when src1 is not presentMatt Turner2017-10-041-1/+1
| | | | | There can be no violation of the restriction that source offsets are aligned if there is only one source offset.
* i965: Remove validate_reg()Matt Turner2017-10-041-80/+0
| | | | | Replaced by the assembly validator, and in fact gets in the way of writing tests for the assembly validator.
* i965: Add and use STRIDE and WIDTH macrosMatt Turner2017-10-041-18/+15
| | | | | | You'll notice there were bugs in some of the code being replaced. Reviewed-by: Iago Toral Quiroga <[email protected]>
* i965: Add parentheses around usage of macro argumentsMatt Turner2017-10-041-1/+1
| | | | | | Otherwise I cannot use this macro in test_eu_validate.cpp Reviewed-by: Iago Toral Quiroga <[email protected]>
* i965: Add GLK, CFL, CNL to test_eu_validate.cMatt Turner2017-10-041-0/+7
|
* i965: Fix support for disassembling 64-bit integer immediatesMatt Turner2017-10-041-2/+2
| | | | | | | The type suffixes were wrong, and the 16 was missing the 0 prefix. Fixes: 92f787ff86ab ("i965: Add support for disassembling 64-bit integer immediates") Reviewed-by: Iago Toral Quiroga <[email protected]>
* i965/fs: Rewrite fsign64 to skip the float -> double conversionMatt Turner2017-10-041-41/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | ... without the float -> double conversion. Low power parts have additional restrictions when it comes to operating on 64-bit types, and the instruction used to do the conversion violates one of them: specifically, the restriction that "Source and Destination horizontal stride must be aligned to the same qword". Previously we generated a float and then converted, but we can avoid the conversion by using the same extract-the-sign-bit + or-in-1.0 algorithm by directly operating on the high four bytes of each double-precision component in the result. In SIMD8 and SIMD16 this cuts one instruction from the implementation, and more importantly that instruction is the one which violated the regioning restriction. Along the way I removed some comments that I did not think helped, and some code about double comparisons which does not seem to be necessary today. This prevents validation failures caught by the new EU validation code added in later patches. Reviewed-by: Iago Toral Quiroga <[email protected]>
* i965/fs: Unpack count argument to 64-bit shift ops on AtomMatt Turner2017-10-041-6/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | 64-bit operations on Atom parts have additional restrictions over their big-core counterparts (validated by later patches). Specifically, the restriction that "Source and Destination horizontal stride must be aligned to the same qword" is violated by most shift operations since NIR uses a 32-bit value as the shift count argument, and this causes instructions like shl(8) g19<1>Q g5<4,4,1>Q g23<4,4,1>UD where src1 has a 32-bit stride, but the dest and src0 have a 64-bit stride. This caused ~4 pixels in the ARB_shader_ballot piglit test fs-readInvocation-uint.shader_test to be incorrect. Unfortunately no ARB_gpu_shader_int64 test hit this case because they operate on uniforms, and their scalar regions are an exception to the restriction. We work around this by effectively unpacking the shift count, so that we can read it with a 64-bit stride in the shift instruction. Unfortunately the unpack (a MOV with a dst stride of 2) is a partial write, and cannot be copy-propagated or CSE'd. Bugzilla: https://bugs.freedesktop.org/101984
* i965/fs: Don't apply POW/FDIV workaround on Gen10+Matt Turner2017-10-041-0/+1
| | | | | | The documentation says it applies only to Gens 8 and 9. Reviewed-by: Scott D Phillips <[email protected]>
* i965: Fix src0 vs src1 typoMatt Turner2017-10-041-1/+1
| | | | | | | | | | | | | | | | A typo caused us to copy src0's reg file to src1 rather than reading src1's as intended. This caused us to fail to compact instructions like mov(8) g4<1>D 0D { align1 1Q }; because src1 was set to immediate rather than architecture file. Fixing this reenables compaction (after the precompact() pass changes the data types): mov(8) g4<1>UD 0x00000000UD { align1 1Q compacted }; Fixes: 1cb0a7941b27 ("i965: Switch to using the logical register types") Reviewed-by: Kenneth Graunke <[email protected]>
* android: fix build issues with brw_nir_trig_workarounds.cTapani Pälli2017-10-041-1/+1
| | | | | | Fixes: 848da66222 ("intel: use a flag instead of setting PYTHONPATH") Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* intel: compiler: vec4: add missing default 0 lodLionel Landwerlin2017-10-031-0/+9
| | | | | | | | | We set a similar default value for LOD in the fs backend for TXS/TXL. Without this we end up generating invalid MOV with a null src. Signed-off-by: Lionel Landwerlin <[email protected]> Cc: "17.2 17.1" <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* anv: Remove base_vertex/instance from push_constantsJason Ekstrand2017-10-031-7/+0
| | | | | | | This is just legacy cruft. We don't push these values; we pass them in as vertex attributes. Reviewed-by: Lionel Landwerlin <[email protected]>
* meson: convert gtest to an internal dependencyDylan Baker2017-10-031-3/+3
| | | | | | | | | | | | In truth gtest is an external dependency that upstream expects you to "vendor" into your own tree. As such, it makes sense to treat it more like a dependency than an internal library, and collect it's requirements together in a dependency object. v2: - include with -isystem instead of setting compiler args (Eric) Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* meson: add window system deps to intel vulkan commonDylan Baker2017-10-031-1/+1
| | | | | Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* intel: Always set Cube Face Enables for all surfaces.Kenneth Graunke2017-10-031-8/+6
| | | | | | | | These shouldn't matter for non-cubes, and we always enable them all for cubes, so we may as well set them all the time. Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel: Make Cube Face Enable fields consistent across generations.Kenneth Graunke2017-10-037-10/+36
| | | | | | | | I decided to use the one-boolean-per-cube-face approach because it's clearer which bits correspond to which cube face. Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* anv: Remove unreachable cases from isl_format_for_size()Józef Kucia2017-10-031-2/+0
| | | | | | | | The dstOffset and fillSize parameters must be multiple of 4. Reviewed-by: Lionel Landwerlin <[email protected] Reviewed-by: Jason Ekstrand <[email protected]> Cc: "17.1 17.2" <[email protected]>
* anv: Fix vkCmdFillBuffer()Józef Kucia2017-10-031-2/+2
| | | | | | | | The vkCmdFillBuffer() command fills a buffer with an uint32_t value. Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Cc: "17.1 17.2" <[email protected]>
* i965: skip reading unused slots at the begining of the URB for the FSIago Toral Quiroga2017-10-022-4/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We can start reading the URB at the first offset that contains varyings that are actually read in the URB. We still need to make sure that we read at least one varying to honor hardware requirements. This helps alleviate a problem introduced with 99df02ca26f61 for separate shader objects: without separate shader objects we assign locations sequentially, however, since that commit we have changed the method for SSO so that the VUE slot assigned depends on the number of builtin slots plus the location assigned to the varying. This fixed layout is intended to help SSO programs by avoiding on-the-fly recompiles when swapping out shaders, however, it also means that if a varying uses a large location number close to the maximum allowed by the SF/FS units (31), then the offset introduced by the number of builtin slots can push the location outside the range and trigger an assertion. This problem is affecting at least the following CTS tests for enhanced layouts: KHR-GL45.enhanced_layouts.varying_array_components KHR-GL45.enhanced_layouts.varying_array_locations KHR-GL45.enhanced_layouts.varying_components KHR-GL45.enhanced_layouts.varying_locations which use SSO and the the location layout qualifier to select such location numbers explicitly. This change helps these tests because for SSO we always have to include things such as VARYING_SLOT_CLIP_DIST{0,1} even if the fragment shader is very unlikely to read them, so by doing this we free builtin slots from the fixed VUE layout and we avoid the tests to crash in this scenario. Of course, this is not a proper fix, we'd still run into problems if someone tries to use an explicit max location and read gl_ViewportIndex, gl_LayerID or gl_CullDistancein in the FS, but that would be a much less common bug and we can probably wait to see if anyone actually runs into that situation in a real world scenario before making the decision that more aggresive changes are required to support this without reverting 99df02ca26f61. v2: - Add a debug message when we skip clip distances (Ilia) - we also need to account for this when we compute the urb setup for the fragment shader stage, so add a compiler util to compute the first slot that we need to read from the URB instead of replicating the logic in both places. v3: - Make the util more generic so it can account for all unused slots at the beginning of the URB, that will make it more useful (Ken). - Drop the debug message, it was not what Ilia was asking for. Suggested-by: Kenneth Graunke <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Normalize types for FBL, FBH, etcMatt Turner2017-09-302-15/+11
| | | | | | | | | | | | Allows the instructions to be compacted. The documentation claims that some of these only accept UD types, even though the type doesn't change the operation performed. Just normalize the types to ensure we get instruction compaction. The only functional changes are for FBL and CBIT (always use UD types) and FBH (always use the same types). Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: force pull model for 64-bit GS inputsIago Toral Quiroga2017-09-292-7/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Triggering the push model when 64-bit inputs are involved is not easy due to the constrains on the maximum number of registers that we allow for this mode, however, for GS with 'points' primitive type and just a couple of double varyings we can trigger this and it just doesn't work because the implementation is not 64-bit aware at all. For now, let's make sure that we don't attempt this model whith 64-bit inputs and we always fall back to pull model for them. Also, don't enable the VUE handles in the thread payload on the fly when we find an input for which we need the pull model, this is not safe: if we need to resort to the pull model we need to account for that when we setup the thread payload so we compute the first non-payload register properly. If we didn't do that correctly and we enable it on-the-fly here then we will end up VUE handles on the first non-payload register which will probably lead to GPU hangs. Instead, always enable the VUE handles for the pull model so we can safely use them when needed. The GS is going to resort to pull model almost in every situation anyway, so this shouldn't make a significant difference and it makes things easier and safer. v2: Always enable the VUE handles for pull model, this is easier and safer and the GS is going to fallback to pull model almost always anyway (Ken) v3: Only clamp the URB read length if we are over the maximum reserved for push inputs as we were doing in the original code (Ken). v4: No need to clamp the urb read length if invocations > 1 Reviewed-by: Kenneth Graunke <[email protected]>
* meson: remove duplicate libisl dependency in anvDylan Baker2017-09-281-1/+1
| | | | | Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* anv: add an assertion in genX(BeginCommandBuffer)Gwan-gyeong Mun2017-09-281-0/+1
| | | | | | | To check a valid usage requirement. Signed-off-by: Mun Gwan-gyeong <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* meson: Add build Intel "anv" vulkan driverDylan Baker2017-09-278-0/+652
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This allows building and installing the Intel "anv" Vulkan driver using meson and ninja, the driver has been tested against the CTS and has seems to pass the same series of tests (they both segfault when the CTS tries to run wayland wsi tests). There are still a mess of TODO, XXX, and FIXME comments in here. Those are mostly for meson bugs I'm trying to fix, or for additional things to implement for other drivers/features. I have configured all intermediate libraries and optional tools to not build by default, meaning they will only be built if they're pulled in as a dependency of a target that will actually be installed) this allows us to avoid massive if chains, while ensuring that only the bits that need to be built are. v2: - enable anv, x11, and wayland by default - add configure option to disable valgrind v3: - fix typo in meson_options (Nicholas) v4: - Remove dead code (Eric) - Remove change to generator that was from v0 (Eric) - replace if chain with loop (Eric) - Fix typos (Eric) - define HAVE_DLOPEN for both libdl and builtin dl cases (Eric) v5: - rebase on util string buffer implementation Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Eric Anholt <[email protected]> (v4)
* intel: use a flag instead of setting PYTHONPATHDylan Baker2017-09-272-9/+26
| | | | | | | | | | | | Meson doesn't allow setting environment variables for custom targets, so we either need to not pass this as an environment variable or use a shell script to wrap the invocation. The chosen solution has the advantage of working for both autotools and meson. v2: - put rules back in top scope (Ken) Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Dylan Baker <[email protected]>
* i965: Support copy propagating of untyped atomic surface indexes.Kenneth Graunke2017-09-261-0/+7
| | | | | | | | In the vec4 backend, SHADER_OPCODE_UNTYPED_ATOMIC's src[1] is the surface index. We want to copy propagate so we can use an immediate message descriptor, rather than an indirect send. Reviewed-by: Ian Romanick <[email protected]>
* i965/vec4: Fix swizzles on atomic sources.Kenneth Graunke2017-09-261-4/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | Atomic operation sources are scalar values, but we were failing to select the .x component of the second operand. For example, atomicCounterCompSwapARB(counter, 5u, 10u) would generate mov(8) vgrf4.x:D, 5D mov(8) vgrf5.x:D, 10D mov(8) vgrf9.x:UD, vgrf4.xyzw:D mov(8) vgrf9.y:UD, vgrf5.xyzw:D which wrongly selects the .y component of vgrf5, so the actual 10u value would get dead code eliminated. The swizzle works for the other source, but both of them ought to be .xxxx. Fixes the compare and swap CTS tests in: KHR-GL45.shader_atomic_counter_ops_tests.ShaderAtomicCounterOpsExchangeTestCase Cc: "17.2 17.1 17.0 13.0" <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965/vec4: Actually handle atomic op intrinsics.Kenneth Graunke2017-09-261-2/+10
| | | | | | | | | | | | Embarassingly, someone enabled the ARB_shader_atomic_counter_ops extension for Gen7+ but never added the intrinsics to the switch statement in the vec4 backend, so they just hit an unreachable() call and died. Fixes: 40dd45d0c6aa4a9d (i965: Enable ARB_shader_atomic_counter_ops) Cc: "17.2 17.1 17.0 13.0" <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* anv: Fix some comment typos.Eric Anholt2017-09-261-3/+3
| | | | Reviewed-by: Jason Ekstrand <[email protected]>
* intel/genxml: Convert a not-present-or-"1" dict to a set.Eric Anholt2017-09-261-2/+3
| | | | | | | I was implementing the same enum support in broadcom's gen_pack_header.py, and did this same simplification there. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/nir: export nir_optimizeTimothy Arceri2017-09-262-7/+11
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Eduardo Lima Mitev <[email protected]>
* anv: fix viewport transformation for z componentSamuel Iglesias Gonsálvez2017-09-251-2/+2
| | | | | | | | | | | | | | | | | | In Vulkan, for 'z' (depth) component, the scale and translate values for the viewport transformation are: pz = maxDepth - minDepth oz = minDepth zf = pz × zd + oz Being zd, the third component in vertex's normalized device coordinates. Fixes: dEQP-VK.draw.inverted_depth_ranges.* Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Cc: [email protected]
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-17 03:50:52 +0000