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* intel/genxml: Make assert in gen_pack_header print a message.Kenneth Graunke2018-05-071-1/+1
| | | | | | | | | | Python's assert can take both a condition and a string, which will cause it to print the string if the assertion trips. (You can't use parens as that creates a tuple.) Doing "condition and string" works in C, but doesn't have the desired effect in Python. Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* anv: remove unused field anv_queue::poolScott D Phillips2018-05-072-3/+0
| | | | | | | The last use of the field was removed in 2015's ("48a87f4ba06 anv/queue: Get rid of the serial") Reviewed-by: Jason Ekstrand <[email protected]>
* intel/genxml: Fix a few invalid field widthsChris Wilson2018-05-076-28/+28
| | | | | | | | | | A couple of typos found by inspecting field.end - field.start, revealed a few wide integers declared as bool and some that ended before they started. Cc: Lionel Landwerlin <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* anv/device: expose shaderInt16 support in gen8+Iago Toral Quiroga2018-05-051-1/+1
| | | | | | | | This rollbacks the revert of this patch introduced with commit 7cf284f18e6774c810ed6db17b98e597bf96f8a5. Tested-by: Mark Janes <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/compiler: handle conversion to smaller type in the lowering pass for thatIago Toral Quiroga2018-05-052-12/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This rollbacks the revert of this same patch introduced in commit 7b9c15628aae8729118b648f5f473e6ac926b99b. And also squahes the following patch to prevent a piglit regression caused by this change: intel/compiler: Fix lower_conversions for 8-bit types. Author: Jose Maria Casanova Crespo <[email protected]> For 8-bit types the execution type is word. A byte raw MOV has 16-bit execution type and 8-bit destination and it shouldn't be considered a conversion case. So there is no need to change alignment and enter in lower_conversions for these instructions. Fixes a regresion in the piglit test "glsl-fs-shader-stencil-export" that is introduced with this patch from the Vulkan shaderInt16 series: 'i965/compiler: handle conversion to smaller type in the lowering pass for that'. The problem is caused because there is already a case in the driver that injects Byte instructions like this: mov(8) g127<1>UB g2<32,8,4>UB And the aforementioned pass was not accounting for the special handling of the execution size of Byte instructions. This patch fixes this. v2: (Jason Ekstrand) - Simplify is_byte_raw_mov, include reference to PRM and not consider B <-> UB conversions as raw movs. v3: (Matt Turner) - Indentation style fixes. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106393 Tested-by: Mark Janes <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/compiler: handle 16-bit to 64-bit conversions in BSW platformsIago Toral Quiroga2018-05-051-4/+4
| | | | | | | | | | | | | | | | | These are subject to the general restriction that anything that is converted to 64-bit needs to be aligned to 64-bit. We had this already in place for 32-bit to 64-bit conversions, so this patch generalizes the implementation to take effect on any conversion to 64-bit from a source smaller than 64-bit. Fixes assembly validation errors in the following CTS tests in BSW: dEQP-VK.spirv_assembly.instruction.compute.sconvert.int16_to_int64 dEQP-VK.spirv_assembly.instruction.compute.uconvert.uint16_to_uint64 dEQP-VK.spirv_assembly.instruction.compute.sconvert.int16_to_uint64 Tested-by: Mark Janes <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/genxml: recognize 0x, 0o and 0b when setting default valueCaio Marcelo de Oliveira Filho2018-05-041-1/+2
| | | | | | | | | | | | | Remove the need of converting values that are documented in hexadecimal. This patch would allow writing <field name="3D Command Sub Opcode" ... default="0x1B"/> instead of <field name="3D Command Sub Opcode" ... default="27"/> Reviewed-by: Lionel Landwerlin <[email protected]>
* Revert "anv/device: expose shaderInt16 support in gen8+"Mark Janes2018-05-031-1/+1
| | | | | | | This reverts commit 0ba0ac815e078185c1f408ec7078fd1efac1a634. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106393 Reviewed-by: Scott D Phillips <[email protected]>
* Revert "i965/compiler: handle conversion to smaller type in the lowering ↵Mark Janes2018-05-032-7/+12
| | | | | | | | | pass for that" This reverts commit 96b51537908cd2aace85f54b437eeb72e6346b7e. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106393 Reviewed-by: Scott D Phillips <[email protected]>
* anv/device: expose shaderInt16 support in gen8+Iago Toral Quiroga2018-05-031-1/+1
| | | | Reviewed-by: Jason Ekstrand <[email protected]>
* anv/pipeline: support SpvCapabilityInt16 in gen8+Iago Toral Quiroga2018-05-031-0/+1
| | | | Reviewed-by: Jason Ekstrand <[email protected]>
* intel/compiler: implement 16-bit pack/unpack opcodesIago Toral Quiroga2018-05-031-0/+10
| | | | Reviewed-by: Jason Ekstrand <[email protected]>
* compiler/lower_64bit_packing: rename the pass to be more genericIago Toral Quiroga2018-05-031-1/+1
| | | | | | It can do 32-bit packing too now. Reviewed-by: Jason Ekstrand <[email protected]>
* intel/compiler: fix 16-bit comparisonsIago Toral Quiroga2018-05-031-8/+30
| | | | | | | | | | | | | | NIR assumes that booleans are always 32-bit, but Intel hardware produces 16-bit booleans for 16-bit comparisons. This means that we need to convert the 16-bit result to 32-bit. In the future we want to add an optimization pass to clean this up and hopefully remove the conversions. v2 (Jason): use the type of the source for the temporary and use brw_reg_type_from_bit_size for the conversion to 32-bit. Reviewed-by: Jason Ekstrand <[email protected]>
* intel/compiler: lower some 16-bit integer operations to 32-bitIago Toral Quiroga2018-05-031-0/+21
| | | | | | | | | These are not supported in hardware for 16-bit integers. We do the lowering pass after the optimization loop to ensure that we lower ALU operations injected by algebraic optimizations too. Reviewed-by: Jason Ekstrand <[email protected]>
* intel/compiler: support negate and abs of half float immediatesJose Maria Casanova Crespo2018-05-031-2/+4
| | | | Reviewed-by: Jason Ekstrand <[email protected]>
* intel/compiler: fix brw_imm_w for negative 16-bit integersJose Maria Casanova Crespo2018-05-031-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | 16-bit immediates need to replicate the 16-bit immediate value in both words of the 32-bit value. This needs to be careful to avoid sign-extension, which the previous implementation was not handling properly. For example, with the previous implementation, storing the value -3 would generate imm.d = 0xfffffffd due to signed integer sign extension, which is not correct. Instead, we should cast to uint16_t, which gives us the correct result: imm.ud = 0xfffdfffd. We only had a couple of cases hitting this path in the driver until now, one with value -1, which would work since all bits are one in this case, and another with value -2 in brw_clip_tri(), which would hit the aforementioned issue (this case only affects gen4 although we are not aware of whether this was causing an actual bug somewhere). v2: Make explicit uint32_t casting for left shift (Jason Ekstrand) Reviewed-by: Jason Ekstrand <[email protected]> Cc: "18.0 18.1" <[email protected]>
* intel/compiler: fix 16-bit int brw_negate_immediate and brw_abs_immediateJose Maria Casanova Crespo2018-05-031-4/+8
| | | | | | | | | | | | | | | | | | | | | From Intel Skylake PRM, vol 07, "Immediate" section (page 768): "For a word, unsigned word, or half-float immediate data, software must replicate the same 16-bit immediate value to both the lower word and the high word of the 32-bit immediate field in a GEN instruction." This fixes the int16/uint16 negate and abs immediates that weren't taking into account the replication in lower and upper words. v2: Integer cases are different to Float cases. (Jason Ekstrand) Included reference to PRM (Jose Maria Casanova) v3: Make explicit uint32_t casting for left shift (Jason Ekstrand) Split half float implementation. (Jason Ekstrand) Fix brw_abs_immediate (Jose Maria Casanova) Cc: "18.0 18.1" <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/compiler: implement nir_instr_type_load_const for 16-bit constantsJose Maria Casanova Crespo2018-05-031-0/+5
| | | | Reviewed-by: Jason Ekstrand <[email protected]>
* intel/compiler: implement conversions from 16-bit int/float to boolIago Toral Quiroga2018-05-031-5/+11
| | | | Reviewed-by: Jason Ekstrand <[email protected]>
* intel/compiler: implement conversion between float/int 16-bit typesIago Toral Quiroga2018-05-031-0/+4
| | | | Reviewed-by: Jason Ekstrand <[email protected]>
* i965/compiler: handle conversion to smaller type in the lowering pass for thatIago Toral Quiroga2018-05-032-12/+7
| | | | | | | The lowering pass was specialized to act on 64-bit to 32-bit conversions only, but the implementation is valid for other cases. Reviewed-by: Jason Ekstrand <[email protected]>
* intel/compiler: fix isign for 16-bit integersIago Toral Quiroga2018-05-031-5/+12
| | | | | | | | | | | | | We need to use 16-bit constants with 16-bit instructions, otherwise we get the following validation error: "Destination stride must be equal to the ratio of the sizes of the execution data type to the destination type" Because the execution data type is 4B due to the 32-bit integer constant. Reviewed-by: Jason Ekstrand <[email protected]>
* intel: aubinator: add an option to limit the number of decoded VBO linesLionel Landwerlin2018-05-021-16/+23
| | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel: decoder: limit to the number decoded lines from VBOLionel Landwerlin2018-05-022-8/+16
| | | | | | | | By default we set no limit, but the debug batch decoder in i965 sets it to 100. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* anv: Advertise variableMultisampleRateJason Ekstrand2018-05-021-1/+1
| | | | | | | | Initially, I didn't understand this feature. Turns out that all it means is that you can switch multisample rates in the middle of a zero-attachment subpass. We've been able to do this since forever. Reviewed-by: Anuj Phogat <[email protected]>
* intel: Fix 3DSTATE_CONSTANT buffer decoding.Kenneth Graunke2018-05-021-15/+25
| | | | | | | | | | First, this was iterating over the 3DSTATE_CONSTANT_* instruction but trying to process fields of the 3DSTATE_CONSTANT_BODY substructure. Secondly, the fields have been called Buffer[0] and Read Length[0], for a while now, and we were not handling the subscripts correctly. Reviewed-by: Lionel Landwerlin <[email protected]>
* intel: fix aubinator includeLionel Landwerlin2018-05-021-1/+1
| | | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Fixes: 7c22c150c40b3 ("intel: Move batch decoder/disassembler from tools/ to common/") Reviewed-by: Kenneth Graunke <[email protected]>
* intel: Give the batch decoder a callback to ask about state size.Kenneth Graunke2018-05-024-6/+28
| | | | | | | | | Given an arbitrary batch, we don't always know what the size of certain things are, such as how many entries are in a binding table. But it's easy for the driver to track that information, so with a simple callback we can calculate this correctly for INTEL_DEBUG=bat. Reviewed-by: Lionel Landwerlin <[email protected]>
* intel: Move batch decoder/disassembler from tools/ to common/Kenneth Graunke2018-05-027-11/+9
| | | | | | | | Making these part of libintel_common allows us to use them in the DRI driver. The standalone tool binaries already link against the common library, too, so it's no harder for them. Reviewed-by: Lionel Landwerlin <[email protected]>
* intel: batch-decoder: iterate VERTEX_BUFFER_STATE fieldsLionel Landwerlin2018-05-021-31/+39
| | | | | | | | | The gen_field_iterator only iterates the fields of a given gen_group. If we want to iterate the fields of another gen_group contained as field, we need to do it manually. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel: decoder: fix starting dword of struct fieldsLionel Landwerlin2018-05-021-2/+3
| | | | | | | | | | | | Struct fields might span several dwords, but iter_dword is incremented up to the last dword of the current field before we print out the struct's fields. We can't use iter_dword for computing the offset into the pointer of data to decode. v2: Fix displayed offset number (Ken) Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel: decoder: document when fields should be usedLionel Landwerlin2018-05-021-3/+2
| | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel: decoder: identify groups with fixed lengthLionel Landwerlin2018-05-022-6/+13
| | | | | | | | | | | | | | <register> & <struct> elements always have fixed length. The get_length() method implies that we're dealing with an instruction in which the length is encoded into the variable data but the field iterator uses it without checking what kind of gen_group it is dealing with. Let's make get_length() report the correct length regardless of the gen_group (register, struct or instruction). Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel: decoder: make the field iterator use more naturalLionel Landwerlin2018-05-022-30/+36
| | | | | | | | | | | while (iter_next()) { ... } instead of do { ... } while (iter_next()); Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel: activate the gl_BaseVertex loweringAntia Puentes2018-05-025-16/+8
| | | | | | | | | | | | | | | | | | | | | | | | | Surplus code related to the basevertex is removed. The Vertex Elements contain now: * VE 1: <firstvertex, BaseInstance, VertexID, InstanceID> * VE 2: <DrawID, is_indexed_draw, 0, 0> Also fixes unreachable message. Fixes OpenGL CTS tests: * KHR-GL46.shader_draw_parameters_tests.ShaderDrawArraysInstancedParameters * KHR-GL46.shader_draw_parameters_tests.ShaderMultiDrawArraysParameters * KHR-GL46.shader_draw_parameters_tests.MultiDrawArraysIndirectCountParameters * KHR-GL46.shader_draw_parameters_tests.ShaderDrawArraysParameters * KHR-GL46.shader_draw_parameters_tests.ShaderMultiDrawArraysIndirectParameters Fixes Piglit tests: * arb_shader_draw_parameters-drawid-indirect baseinstance * arb_shader_draw_parameters-basevertex Reviewed-by: Jason Ekstrand <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102678
* intel: emit is_indexed_draw in the same VE than gl_DrawIDAntia Puentes2018-05-023-8/+19
| | | | | | | | | | | The Vertex Elements are now: * VE 1: <BaseVertex/firstvertex, BaseInstance, VertexID, InstanceID> * VE 2: <DrawID, is-indexed-draw, 0, 0> VE1 is it kept as it was before, VE2 additionally contains the new system value. Reviewed-by: Jason Ekstrand <[email protected]>
* intel/compiler: Add uses_is_indexed_draw flagAntia Puentes2018-05-022-0/+5
| | | | Reviewed-by: Jason Ekstrand <[email protected]>
* anv: Allow lookup of vkEnumerateInstanceVersion without an instanceJason Ekstrand2018-05-011-0/+1
| | | | | Fixes: cbab2d1da5edfe9df27a010adf8b1aa9dbee473b Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* anv: Don't advertise Float64 or Int64 on HW without 64-bit typesJason Ekstrand2018-05-011-2/+4
| | | | Reviewed-by: Anuj Phogat <[email protected]>
* intel: fix check for 48b ppgtt supportScott D Phillips2018-04-304-48/+19
| | | | | | | | | | | | | | | | | The previous logic of the supports_48b_addresses wasn't actually checking if i915.ko was running with full_48bit_ppgtt. The ENOENT it was checking for was actually coming from the invalid context id provided in the test execbuffer. There is no path in the kernel driver where the presence of EXEC_OBJECT_SUPPORTS_48B_ADDRESS leads to an error. Instead, check the default context's GTT_SIZE param for a value greater than 4 GiB v2 (Ken): Fix in i965 as well. v3 Check GTT_SIZE instead of HAS_ALIASING_PPGTT (Chris Wilson) Reviewed-by: Kenneth Graunke <[email protected]>
* meson: fix race condition revealed by using 0.44Dylan Baker2018-04-271-3/+3
| | | | | | | | | | | | | | | | | | Previously there was a special target that blocked for the generation of anv_entrypoints.h, with meson 0.44 we don't need this, we can use a new language feature instead. The problem is that previously that blocking target would hide a race condition for the generation of another header, anv_extensions.h. Now the build sometimes fails when anv_extensions.h is not generated in time. v2: - clarify the race condition in the commit message (Emil) CC: Mark Janes <[email protected]> Fixes: 92550d9b16d2b295bdac087f31b1fd6d0f808e02 ("meson: remove workaround for custom target creating .h and .c files") Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Scott D Phillips <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* anv/icl: Enable Vulkan on Ice LakeAnuj Phogat2018-04-261-0/+2
| | | | | | | | This patch enables the Vulkan driver on Ice Lake h/w with added warning about preliminary support. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Nanley Chery <[email protected]>
* anv: enable VK_EXT_shader_viewport_index_layerCaio Marcelo de Oliveira Filho2018-04-262-0/+2
| | | | | Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* anv/allocator: Don't shrink either end of the block poolJason Ekstrand2018-04-261-4/+4
| | | | | | | | | | | | | Previously, we only tried to ensure that we didn't shrink either end below what was already handed out. However, due to the way we handle relocations with block pools, we can't shrink the back end at all. It's probably best to not shrink in either direction. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105374 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106147 Tested-by: Eero Tamminen <[email protected]> Reviewed-by: Scott D Phillips <[email protected]> Cc: [email protected]
* meson: remove dummy_cppDylan Baker2018-04-241-1/+1
| | | | | | | | | | meson has gotten pretty smart about tracking C and C++ dependencies (internal and external), and using the right linker. This wasn't always the case and we created empty c++ files to force the use of the c++ linker. We don't need that any more. Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* meson: remove workaround for custom target creating .h and .c filesDylan Baker2018-04-241-13/+4
| | | | | | | | | In more modern versions of meson a custom_target returns an index-able object. This allows us to create accurate dependency models for targets that rely only on the header and not on the code from anv_entrypoints. Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* intel/compiler: Add scheduler deps for instructions that implicitly read g0Ian Romanick2018-04-242-0/+28
| | | | | | | | | | | | | Otherwise the scheduler can move the writes after the reads. Signed-off-by: Ian Romanick <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95009 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95012 Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Tested-by: Mark Janes <[email protected]> Cc: Clayton A Craft <[email protected]> Cc: [email protected]
* intel/compiler: Silence unused parameter warnings in empty ↵Ian Romanick2018-04-241-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | vec4_instruction_scheduler methods src/intel/compiler/brw_schedule_instructions.cpp: In member function ‘virtual void vec4_instruction_scheduler::count_reads_remaining(backend_instruction*)’: src/intel/compiler/brw_schedule_instructions.cpp:764:72: warning: unused parameter ‘be’ [-Wunused-parameter] vec4_instruction_scheduler::count_reads_remaining(backend_instruction *be) ^~ src/intel/compiler/brw_schedule_instructions.cpp: In member function ‘virtual void vec4_instruction_scheduler::setup_liveness(cfg_t*)’: src/intel/compiler/brw_schedule_instructions.cpp:769:51: warning: unused parameter ‘cfg’ [-Wunused-parameter] vec4_instruction_scheduler::setup_liveness(cfg_t *cfg) ^~~ src/intel/compiler/brw_schedule_instructions.cpp: In member function ‘virtual void vec4_instruction_scheduler::update_register_pressure(backend_instruction*)’: src/intel/compiler/brw_schedule_instructions.cpp:774:75: warning: unused parameter ‘be’ [-Wunused-parameter] vec4_instruction_scheduler::update_register_pressure(backend_instruction *be) ^~ src/intel/compiler/brw_schedule_instructions.cpp: In member function ‘virtual int vec4_instruction_scheduler::get_register_pressure_benefit(backend_instruction*)’: src/intel/compiler/brw_schedule_instructions.cpp:779:80: warning: unused parameter ‘be’ [-Wunused-parameter] vec4_instruction_scheduler::get_register_pressure_benefit(backend_instruction *be) ^~ src/intel/compiler/brw_schedule_instructions.cpp: In member function ‘virtual int vec4_instruction_scheduler::issue_time(backend_instruction*)’: src/intel/compiler/brw_schedule_instructions.cpp:1550:61: warning: unused parameter ‘inst’ [-Wunused-parameter] vec4_instruction_scheduler::issue_time(backend_instruction *inst) ^~~~ Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/compiler: Silence unused parameter warning in compile_cs_to_nirIan Romanick2018-04-241-4/+3
| | | | | | | | | | src/intel/compiler/brw_fs.cpp: In function ‘nir_shader* compile_cs_to_nir(const brw_compiler*, void*, const brw_cs_prog_key*, brw_cs_prog_data*, const nir_shader*, unsigned int)’: src/intel/compiler/brw_fs.cpp:7205:44: warning: unused parameter ‘prog_data’ [-Wunused-parameter] struct brw_cs_prog_data *prog_data, ^~~~~~~~~ Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
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