summaryrefslogtreecommitdiffstats
path: root/src/intel
Commit message (Expand)AuthorAgeFilesLines
* anv/image: Use align_u64 for image offsetsJason Ekstrand2020-04-091-2/+2
* anv/pipeline: allow more than 16 FS inputsJuan A. Suarez Romero2020-04-091-14/+21
* intel/compiler: store the FS inputs in WM prog dataJuan A. Suarez Romero2020-04-092-0/+6
* i965: Move down genX_upload_sbe in profiles.Mathias Fröhlich2020-04-094-0/+34
* anv: Account for the header in anv_state_stream_allocJason Ekstrand2020-03-311-2/+3
* intel/fs/gen12: Fix interaction of SWSB dependency combination with EU fusion...Francisco Jerez2020-03-301-10/+11
* isl: drop min row pitch alignment when set by the driverLionel Landwerlin2020-03-201-1/+9
* isl: only apply main surface ccs pitch constraint with CCSLionel Landwerlin2020-03-201-1/+2
* isl: properly filter supported display modifiers on Gen9+Lionel Landwerlin2020-03-201-3/+13
* isl: implement linear tiling row pitch requirement for displayLionel Landwerlin2020-03-201-3/+14
* anv: Swizzle fast-clear valuesJason Ekstrand2020-03-193-9/+19
* intel/blorp: Add support for swizzling fast-clear colorsJason Ekstrand2020-03-193-4/+12
* anv: Do an end-of-pipe sync before updating AUX table entriesJason Ekstrand2020-03-181-1/+1
* anv: Wait for the GPU to be idle before invalidating the aux table.Rafael Antognolli2020-03-181-0/+10
* anv: Do end-of-pipe sync around MCS/CCS ops instead of CS stallJason Ekstrand2020-03-182-8/+8
* anv: Use a proper end-of-pipe sync instead of just CS stallJason Ekstrand2020-03-182-15/+118
* anv: Use the PIPE_CONTROL instead of bits for the CS stall W/AJason Ekstrand2020-03-181-3/+7
* intel/fs: Fix workaround for VxH indirect addressing bug under control flow.Francisco Jerez2020-03-101-10/+28
* anv: Parse VkPhysicalDeviceFeatures2 in CreateDeviceJason Ekstrand2020-03-101-10/+45
* isl: Set 3DSTATE_DEPTH_BUFFER::Depth correctly for 3D surfacesJason Ekstrand2020-03-061-1/+19
* intel/gen12+: Disable mid thread preemption.Rafael Antognolli2020-03-042-0/+13
* intel/device: bdw_gt1 actually has 6 eus per subslicePaulo Zanoni2020-03-041-1/+1
* intel: fix the gen 12 compute shader scratch IDsPaulo Zanoni2020-03-041-3/+8
* intel: fix the gen 11 compute shader scratch IDsPaulo Zanoni2020-03-041-1/+6
* intel/compiler: Restrict cs_threads to 64Jordan Justen2020-03-021-1/+3
* anv: Always enable the data cacheJason Ekstrand2020-02-283-10/+1
* intel/fs: Correctly handle multiply of fsign with a source modifierIan Romanick2020-02-201-0/+10
* intel/gen12: Take into account opcode when decoding SWSBCaio Marcelo de Oliveira Filho2020-02-202-3/+7
* intel/fs/gen12: Workaround data coherency issues due to broken NoMask control...Francisco Jerez2020-02-181-34/+100
* intel/fs/gen12: Fixup/simplify SWSB annotations of SIMD32 scratch writes.Francisco Jerez2020-02-181-7/+3
* intel/fs/gen12: Workaround unwanted SEND execution due to broken NoMask contr...Francisco Jerez2020-02-182-0/+150
* intel/fs: Add virtual instruction to load mask of live channels into flag reg...Francisco Jerez2020-02-185-2/+22
* intel/fs/gen7: Fix fs_inst::flags_written() for SHADER_OPCODE_FIND_LIVE_CHANNEL.Francisco Jerez2020-02-181-1/+2
* intel/fs/cse: Make HALT instruction act as CSE barrier.Francisco Jerez2020-02-181-0/+10
* intel/vec4: fix valgrind errors with vf_values arrayTapani Pälli2020-02-071-1/+2
* anv: set MOCS on push constantsLionel Landwerlin2020-02-071-1/+7
* intel: Load the driver even if I915_PARAM_REVISION is not found.Rafael Antognolli2020-02-071-1/+1
* intel/fs: Don't count integer instructions as being possibly coissueIan Romanick2020-02-051-1/+8
* anv: implement gen9 post sync pipe control workaroundLionel Landwerlin2020-02-053-0/+39
* anv/blorp: Use the correct size for vkCmdCopyBufferToImageJason Ekstrand2020-02-031-0/+8
* intel/fs: Write the address register with NoMask for MOV_INDIRECTJason Ekstrand2020-02-031-0/+9
* anv: Always fill out the AUX table even if CCS is disabledJason Ekstrand2020-01-313-16/+18
* anv: Plumb deref block size through to 3DSTATE_SFJason Ekstrand2020-01-314-11/+18
* intel/blorp: Plumb deref block size through to 3DSTATE_SFJason Ekstrand2020-01-311-6/+10
* intel/common: Return the block size from get_urb_configJason Ekstrand2020-01-314-4/+51
* anv: Emit URB setup earlierJason Ekstrand2020-01-311-2/+2
* intel/blorp: Always emit URB config on Gen7+Jason Ekstrand2020-01-312-20/+46
* intel: Take a gen_l3_config in gen_get_urb_configJason Ekstrand2020-01-313-15/+11
* intel/genxml: Drop SLMEnable from L3CNTLREG on Gen11Jason Ekstrand2020-01-312-2/+1
* anv,iris: Set 3DSTATE_SF::DerefBlockSize to per-poly on Gen12+Jason Ekstrand2020-01-312-1/+9