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* anv/cmd_buffer: Take bo_offset into account in fast clear state addressesJason Ekstrand2017-11-171-1/+1
* anv/cmd_buffer: Advance the address when initializing clear colorsJason Ekstrand2017-11-171-3/+6
* Revert "intel/fs: Use a pure vertical stride for large register strides"Matt Turner2017-11-171-13/+3
* i965/fs: Split all 32->64-bit MOVs on CHV, BXT, GLKMatt Turner2017-11-171-4/+4
* i965/fs: Fix extract_i8/u8 to a 64-bit destinationMatt Turner2017-11-171-2/+23
* intel/tools: Fix detection of enabled shader stages.Kenneth Graunke2017-11-171-1/+1
* intel/blorp: Make the MOCS setting part of blorp_addressJason Ekstrand2017-11-174-18/+18
* anv/blorp: Add a device parameter to blorp_surf_for_anv_imageJason Ekstrand2017-11-171-22/+34
* intel/blorp: Use mocs.tex for depth stencilJason Ekstrand2017-11-171-5/+1
* autotools: Set C++ visibility flags on IntelDylan Baker2017-11-131-0/+3
* automake: intel: correctly append to the LIBADD variableEmil Velikov2017-11-131-1/+1
* intel/nir: Use the correct indirect lowering masks in link_shadersJason Ekstrand2017-11-101-6/+4
* intel/nir: Break the linking code into a helper in brw_nir.cJason Ekstrand2017-11-102-0/+36
* intel/nir: Add a helper for getting the NoIndirect maskJason Ekstrand2017-11-101-14/+19
* intel/fs: Rework zero-length URB write handlingJason Ekstrand2017-11-101-29/+31
* intel/fs: Mark 64-bit values as being contiguousJason Ekstrand2017-11-101-1/+4
* intel/fs: Fix integer multiplication lowering for src/dst hazardsJason Ekstrand2017-11-101-2/+8
* intel/fs: Fix MOV_INDIRECT for 64-bit values on little-coreJason Ekstrand2017-11-101-36/+39
* intel/eu/reg: Add a subscript() helperJason Ekstrand2017-11-101-0/+16
* intel/fs: Use a pair of 1-wide MOVs instead of SEL for any/allJason Ekstrand2017-11-101-9/+33
* intel/fs: Use an explicit D type for vote any/all/eq intrinsicsJason Ekstrand2017-11-101-0/+6
* intel/fs: Don't stomp f0.1 in SIMD16 ballotJason Ekstrand2017-11-101-2/+9
* intel/fs: Use ANY/ALL32 predicates in SIMD32Jason Ekstrand2017-11-101-12/+30
* intel/fs: Be more explicit about our placement of [un]zipJason Ekstrand2017-11-101-3/+17
* intel/fs: Pass builders instead of blocks into emit_[un]zipJason Ekstrand2017-11-101-26/+35
* intel/fs: Use a pure vertical stride for large register stridesJason Ekstrand2017-11-101-3/+13
* intel/fs: Alloc pull constants off mem_ctxJason Ekstrand2017-11-031-1/+1
* i965: fix blorp stage_prog_data->param leakTapani Pälli2017-11-031-1/+1
* intel/compiler/gen9: Pixel shader header only workaroundTopi Pohjolainen2017-11-031-0/+29
* intel/eu: Use EXECUTE_1 for JMPIJason Ekstrand2017-10-272-2/+1
* i965: Fix memmem compiler warnings.Eric Anholt2017-10-271-1/+2
* anv/pipeline: Call nir_lower_system_valaues after brw_preprocess_nirJason Ekstrand2017-10-271-1/+2
* anv/pipeline: Drop nir_lower_clip_cull_distance_arraysJason Ekstrand2017-10-271-2/+0
* intel/fs: Handle flag read/write aliasing in needs_src_copyJason Ekstrand2017-10-271-1/+3
* anv: don't assert on device init on CannonlakeLionel Landwerlin2017-10-211-2/+4
* anv: disable stencil pma fix on Gen > 9Lionel Landwerlin2017-10-211-0/+2
* blorp: enable R32G32B32X32 blorp ccs copiesLionel Landwerlin2017-10-211-0/+1
* i965/fs: Use align1 mode on ternary instructions on Gen10+Matt Turner2017-10-201-4/+8
* i965: Add align1 ternary instruction emission supportMatt Turner2017-10-201-55/+160
* i965: Add align1 ternary instruction disassembler supportMatt Turner2017-10-202-75/+288
* i965: Add align1 ternary instruction-word supportMatt Turner2017-10-201-0/+108
* i965: Add align1 ternary instruction support to conversion functionsMatt Turner2017-10-204-34/+101
* i965: Add align1 ternary instruction field encodingsMatt Turner2017-10-201-0/+35
* i965: Add functions to abstract access to 3src register typesMatt Turner2017-10-202-20/+23
* i965: Rename brw_inst's functions that access the 3src register typeMatt Turner2017-10-203-18/+18
* i965: Rename brw_inst 3src functions in preparation for align1Matt Turner2017-10-204-86/+92
* i965: Print subreg in units of type-size on ternary instructionsMatt Turner2017-10-201-5/+26
* i965: Add functions for brw_reg_type <-> hw 3src typeMatt Turner2017-10-202-0/+58
* i965: Move brw_reg_type_is_floating_point to brw_reg_type.hMatt Turner2017-10-202-13/+15
* nir: Get rid of nir_shader::stageJason Ekstrand2017-10-2011-37/+38
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