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* intel: Use 3DSTATE_DEPTH_BUFFER::ControlSurfaceEnableNanley Chery2019-10-282-1/+2
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* intel/isl: Support HIZ_CCS in emit_depth_stencil_hizJason Ekstrand2019-10-281-2/+10
| | | | | | | v2. Remove undocumented CCS_E-only mode for depth. (Nanley) Co-authored-by: Nanley Chery <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel: Use RENDER_SURFACE_STATE::DepthStencilResourceNanley Chery2019-10-282-0/+6
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* intel: Update alignment restrictions for HiZ surfaces.Jordan Justen2019-10-281-1/+7
| | | | | | | | | v2 (Nanley): * Maintain a chronological ordering for HiZ alignments. Suggested by Ken. Co-authored-by: Nanley Chery <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/blorp: Disable depth testing for slow depth clearsNanley Chery2019-10-281-5/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We'll start doing slow depth clears more often on HIZ_CCS buffers in a future commit. Reduce the performance impact by making them use less bandwidth. From the Depth Test section of the BSpec: This function is enabled by the Depth Test Enable state variable. If enabled, the pixel's ("source") depth value is first computed. After computation the pixel's depth value is clamped to the range defined by Minimum Depth and Maximum Depth in the selected CC_VIEWPORT state. Then the current ("destination") depth buffer value for this pixel is read. and from the Depth Buffer Updates section of the BSpec: If depth testing is disabled or the depth test passed, the incoming pixel's depth value is written to the Depth Buffer. Taken together, it's clear that depth testing isn't necessary to perform a depth buffer clear. Mark Janes and I analyzed this patch with frameretrace and a depthrange piglit test. I disabled HiZ to ensure we'd get slow depth clears. We've observed the bandwidth consumption by the depth buffer access to be cut ~50% on BDW and SKL during depth clears. On a more graphically intensive workload, the Shadowmapping Sascha benchmark, I took the average of 3 runs on a BDW with a display resolution of about 1920x1200 (minus some desktop environment decorations). I measured a 22.61% FPS improvement when HiZ is disabled. v2. The BSpec doesn't mandate this behavior, update comment accordingly. (Ken) Fixes: bc4bb5a7e30 ("intel/blorp: Emit more complete DEPTH_STENCIL state") Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel: Enable CCS_E for some formats on Gen12Nanley Chery2019-10-282-29/+64
| | | | | | | | | | | | | | | | | In ISL: Update the format table to add CCS_E support for some 8BPP formats, some 16BPP formats, and R10G10B10A2_UNORM_SRGB. In the helper for determining CCS_E support, we return false for some 16BPP formats because they aren't properly handled in blorp_copy(). In BLORP: Allow the new and non-problematic formats for CCS_E-enabled copies. v2. Update other fields for A1B5G5R5_UNORM and A4B4G4R4_UNORM in table. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]> (v1)
* isl: Redefine the CCS layout for Gen12Nanley Chery2019-10-285-15/+136
| | | | | | | | | | | The CCS could be described in a number of ways, but this format was chosen to minimize churn in the drivers. We may decide on an different direction in the future. v2. Increase alignment for display surfaces. (Nanley) Reviewed-by: Jordan Justen <[email protected]> (v1) Acked-by: Kenneth Graunke <[email protected]>
* isl: Add and use isl_tiling_flag_to_enum()Nanley Chery2019-10-282-2/+9
| | | | | | | | Use a helper that will automatically handle Gen12's CCS tiling when creating a CCS isl_surf. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* isl/drm: Map HiZ and CCS tilings to YNanley Chery2019-10-281-2/+2
| | | | | | | | | In the function which translates ISL tilings to i915 tilings, map ISL's HiZ and CCS tilings to Y instead of NONE (linear). The HW docs describe HiZ and pre-Gen12 CCS surfaces as being Y-tiled in memory. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* intel/isl: Update surf_fill_state for gen12Jason Ekstrand2019-10-281-4/+22
| | | | | | | | | | v2 (Nanley): * Avoid driver churn for now. * Include some media compression changes. Co-authored-by: Nanley Chery <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* intel/isl/fill_state: Separate aux_mode handling from aux_surfJason Ekstrand2019-10-281-20/+41
| | | | | | | | v2. Avoid driver churn for now. (Nanley) Co-authored-by: Nanley Chery <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* intel/isl: Add new aux modes available on gen12Jason Ekstrand2019-10-281-1/+33
| | | | | | | | v2. Add media compression. (Nanley) Co-authored-by: Nanley Chery <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* anv/private: Modify aux slice helpers for Gen12 CCSNanley Chery2019-10-281-3/+17
| | | | | | | | | | | The isl_surf structs for Gen12's CCS won't describe how many slices in the main surface can be compressed. All slices will be compressable if CCS is enabled, so lookup the main surface's logical dimension. v2. Add a space before a `?`. (Jordan) Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* intel/blorp: Don't assert aux slices match main slicesNanley Chery2019-10-282-8/+0
| | | | | | | | | This isn't accurate enough for HiZ which can have a discontiguous range of supported aux slices. This also won't work with the plan to represent Gen12 CCS as a single slice surface. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* intel/blorp: Use surf instead of aux_surf for image dimensionsJason Ekstrand2019-10-281-2/+2
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* intel/blorp: Halve the Gen12 fast-clear/resolve rectangleNanley Chery2019-10-281-4/+9
| | | | | | | Update their dimensions according to the Bspec. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* intel/blorp/gen12: Set FWCC when storing the clear color.Rafael Antognolli2019-10-282-0/+5
| | | | | | | | | | | | | | | | | | | | From "Render Target Fast Clear" description for Gen12: "SW must store clear color using MI_STORE_DATA_IMM with ForceWriteCompletionCheck bit set." From Instruction_MI_STORE_DATA_IMM, bitfield 10 (when set to 1): "Following the last write from this command, Command Streamer will wait for all previous writes are completed and in global observable domain before moving to next command." We use 4 SDIs to store the clear color (one per channel). From the description, it looks to me that setting that flag only on the last SDI should be enough. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* isl: Round up some pitches to 512B for Gen12's CCSNanley Chery2019-10-281-6/+14
| | | | | | | | | Gen12's CCS requires that the main surface have a pitch aligned to 512B. v2. Provide a BSpec citation. (Ken) Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* anv/cmd_buffer: Don't assume CCS_E includes CCS_DNanley Chery2019-10-281-1/+2
| | | | | | There's no longer a clear-only compression mode of CCS on Gen12+. Reviewed-by: Kenneth Graunke <[email protected]>
* anv/image: Disable CCS_D on Gen12+Nanley Chery2019-10-281-0/+6
| | | | | | | | Clear-only compression no longer exists on TGL. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Sagar Ghuge <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* isl: Disable CCS_D on Gen12+Nanley Chery2019-10-281-2/+4
| | | | | | | | | | Clear-only compression no longer exists on TGL. v2. Add BSpec reference. (Sagar) Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Sagar Ghuge <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* anv/formats: Disable I915_FORMAT_MOD_Y_TILED_CCS on TGL+Nanley Chery2019-10-281-0/+5
| | | | | | | The format of the CCS has changed. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* anv: Properly allocate aux-tracking space for CCS_ENanley Chery2019-10-282-3/+5
| | | | | | | | | add_aux_state_tracking_buffer() actually checks the aux usage when determining how many dwords to allocate for state tracking. Move the function call to the point after the CCS_E aux usage is assigned. Fixes: de3be618016 ("anv/cmd_buffer: Rework aux tracking") Reviewed-by: Kenneth Graunke <[email protected]>
* anv/blorp: Use BLORP_BATCH_NO_UPDATE_CLEAR_COLORNanley Chery2019-10-281-22/+10
| | | | | | | | Avoid failing the `info->use_clear_address` assertion in ISL on Gen12+. Fixes: 6c9f9a82d78 ("intel/genxml,isl: Add gen12 render surface state changes") Reported-by: Caio Marcelo de Oliveira Filho <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* anv: Add support for depth bounds testing.Plamena Manolova2019-10-283-0/+15
| | | | | | | | In gen12 we use the 3DSTATE_DEPTH_BOUNDS instruction to enable depth bounds testing. Signed-off-by: Plamena Manolova <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* genxml: Add 3DSTATE_DEPTH_BOUNDS instruction.Plamena Manolova2019-10-281-0/+13
| | | | | | | | In gen12 we add the 3DSTATE_DEPTH_BOUNDS instruction which enables support for depth bounds testing. Signed-off-by: Plamena Manolova <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* util: rename list_empty() to list_is_empty()Timothy Arceri2019-10-284-7/+7
| | | | | | | This makes it clear that it's a boolean test and not an action (eg. "empty the list"). Reviewed-by: Eric Engestrom <[email protected]>
* intel/compiler: Fix C++ one definition rule violationsDanylo Piliaiev2019-10-284-20/+20
| | | | | | | | When building with "-flto" brw::block_data definitions were colliding. Signed-off-by: Danylo Piliaiev <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* isl/gen12: 64k surface alignmentJordan Justen2019-10-281-0/+4
| | | | | | | | Reworks: * Update size for aux map change (Nanley) Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* anv: Add aux-map translation for gen12+Lionel Landwerlin2019-10-282-0/+44
| | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* anv/gen12: Write GFX_AUX_TABLE base address registerJordan Justen2019-10-284-0/+44
| | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* genxml/gen12: Add AUX MAP register definitionsJordan Justen2019-10-281-0/+8
| | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* anv/gen12: Initialize aux map contextJordan Justen2019-10-282-2/+22
| | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/common: Add surface to aux map translation table supportJordan Justen2019-10-284-0/+665
| | | | | | | | | | | | | Reworks: * Add ISL_FORMAT_B8G8R8X8_UNORM_SRGB to get_format_encoding (Nanley) * ralloc_free aux_map_buffer entries in gen_aux_map_finish. (Rafael) * verify_aligned_space => align_and_verify_space (Rafael) * Add mutex to aux-map code. (Rafael, Nanley) * Add gen_aux_map_fill_bos (Ken) * Make gen_aux_map_get_state_num lockless Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* anv: Implement aux-map allocator interfaceJordan Justen2019-10-281-0/+42
| | | | | | | | | | | This interface allows the aux-map code in the intel/common library to allocate and free buffers. Reworks: * free gen_buffer in gen_aux_map_buffer_free. (Rafael) Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/common: Add interface to allocate device buffersJordan Justen2019-10-283-0/+51
| | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/dev: store whether the device uses an aux map tables on devinfoLionel Landwerlin2019-10-281-0/+1
| | | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* anv: fix empty-body instructionEric Engestrom2019-10-271-1/+1
| | | | | | | Fixes: 8d43e2b2ded0fe3c82d4 ("meson: add -Werror=empty-body to disallow `if(x);`") Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* anv: Implement VK_KHR_vulkan_memory_modelCaio Marcelo de Oliveira Filho2019-10-243-0/+12
| | | | Reviewed-by: Jason Ekstrand <[email protected]>
* intel/fs: Implement scoped_memory_barrierCaio Marcelo de Oliveira Filho2019-10-241-8/+19
| | | | Reviewed-by: Jason Ekstrand <[email protected]>
* intel/fs: Check for NULL key in fs_visitor constructorMichel Dänzer2019-10-241-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | Flagged by UBSan: ../src/intel/compiler/brw_fs_visitor.cpp:986:20: runtime error: member access within null pointer of type 'const struct brw_base_prog_key' #0 0x559fadb48556 in fs_visitor::init() ../src/intel/compiler/brw_fs_visitor.cpp:986 #1 0x559fadb46db3 in fs_visitor::fs_visitor(brw_compiler const*, void*, void*, brw_base_prog_key const*, brw_stage_prog_data*, nir_shader const*, unsigned int, int, brw_vue_map const*) ../src/intel/compiler/brw_fs_visitor.cpp:962 #2 0x559fad9c7cd8 in saturate_propagation_fs_visitor::saturate_propagation_fs_visitor(brw_compiler*, brw_wm_prog_data*, nir_shader*) (/home/daenzer/src/mesa-git/mesa/build-amd64-sanitize/src/intel/compiler/fs_saturate_propagation+0x61bcd8) #3 0x559fad9960a1 in saturate_propagation_test::SetUp() ../src/intel/compiler/test_fs_saturate_propagation.cpp:65 #4 0x559fadd7a32d in void testing::internal::HandleSehExceptionsInMethodIfSupported<testing::Test, void>(testing::Test*, void (testing::Test::*)(), char const*) ../src/gtest/src/gtest.cc:2402 #5 0x559fadd65c3b in void testing::internal::HandleExceptionsInMethodIfSupported<testing::Test, void>(testing::Test*, void (testing::Test::*)(), char const*) ../src/gtest/src/gtest.cc:2438 #6 0x559fadd0af75 in testing::Test::Run() ../src/gtest/src/gtest.cc:2470 #7 0x559fadd0d8a4 in testing::TestInfo::Run() ../src/gtest/src/gtest.cc:2656 #8 0x559fadd10032 in testing::TestCase::Run() ../src/gtest/src/gtest.cc:2774 #9 0x559fadd2ba0c in testing::internal::UnitTestImpl::RunAllTests() ../src/gtest/src/gtest.cc:4649 #10 0x559fadd7df46 in bool testing::internal::HandleSehExceptionsInMethodIfSupported<testing::internal::UnitTestImpl, bool>(testing::internal::UnitTestImpl*, bool (testing::internal::UnitTestImpl::*)(), char const*) ../src/gtest/src/gtest.cc:2402 #11 0x559fadd69613 in bool testing::internal::HandleExceptionsInMethodIfSupported<testing::internal::UnitTestImpl, bool>(testing::internal::UnitTestImpl*, bool (testing::internal::UnitTestImpl::*)(), char const*) ../src/gtest/src/gtest.cc:2438 #12 0x559fadd2302e in testing::UnitTest::Run() ../src/gtest/src/gtest.cc:4257 #13 0x559fadda2d61 in RUN_ALL_TESTS() ../src/gtest/include/gtest/gtest.h:2233 #14 0x559fadda2c21 in main ../src/gtest/src/gtest_main.cc:37 #15 0x7fe8f6748bba in __libc_start_main ../csu/libc-start.c:308 #16 0x559fad9950f9 in _start (/home/daenzer/src/mesa-git/mesa/build-amd64-sanitize/src/intel/compiler/fs_saturate_propagation+0x5e90f9) Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Adam Jackson <[email protected]>
* intel/compiler: Cast to target type before shifting leftMichel Dänzer2019-10-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | Otherwise a smaller type may be promoted to int, which can hit undefined behaviour: ../src/intel/compiler/brw_packed_float.c:66:17: runtime error: left shift of 128 by 24 places cannot be represented in type 'int' #0 0x5604a03969aa in brw_vf_to_float ../src/intel/compiler/brw_packed_float.c:66 #1 0x5604a0391305 in vf_float_conversion_test_test_vf_to_float_Test::TestBody() ../src/intel/compiler/test_vf_float_conversions.cpp:70 #2 0x5604a041a323 in void testing::internal::HandleSehExceptionsInMethodIfSupported<testing::Test, void>(testing::Test*, void (testing::Test::*)(), char const*) ../src/gtest/src/gtest.cc:2402 #3 0x5604a0405c31 in void testing::internal::HandleExceptionsInMethodIfSupported<testing::Test, void>(testing::Test*, void (testing::Test::*)(), char const*) ../src/gtest/src/gtest.cc:2438 #4 0x5604a03ab03b in testing::Test::Run() ../src/gtest/src/gtest.cc:2474 #5 0x5604a03ad714 in testing::TestInfo::Run() ../src/gtest/src/gtest.cc:2656 #6 0x5604a03afea2 in testing::TestCase::Run() ../src/gtest/src/gtest.cc:2774 #7 0x5604a03cb87c in testing::internal::UnitTestImpl::RunAllTests() ../src/gtest/src/gtest.cc:4649 #8 0x5604a041df3c in bool testing::internal::HandleSehExceptionsInMethodIfSupported<testing::internal::UnitTestImpl, bool>(testing::internal::UnitTestImpl*, bool (testing::internal::UnitTestImpl::*)(), char const*) ../src/gtest/src/gtest.cc:2402 #9 0x5604a0409609 in bool testing::internal::HandleExceptionsInMethodIfSupported<testing::internal::UnitTestImpl, bool>(testing::internal::UnitTestImpl*, bool (testing::internal::UnitTestImpl::*)(), char const*) ../src/gtest/src/gtest.cc:2438 #10 0x5604a03c2e9e in testing::UnitTest::Run() ../src/gtest/src/gtest.cc:4257 #11 0x5604a0442d57 in RUN_ALL_TESTS() ../src/gtest/include/gtest/gtest.h:2233 #12 0x5604a0442c17 in main ../src/gtest/src/gtest_main.cc:37 #13 0x7f9a1983dbba in __libc_start_main ../csu/libc-start.c:308 #14 0x5604a0390d89 in _start (/home/daenzer/src/mesa-git/mesa/build-amd64-sanitize/src/intel/compiler/vf_float_conversions+0x8dd89) Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Adam Jackson <[email protected]>
* intel/compiler: Don't left-shift by >= the number of bits of the typeMichel Dänzer2019-10-241-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | To avoid it, use the modulo of the number of bits in the value being shifted, which is presumably what ended up happening on x86. Flagged by UBSan: ../src/intel/compiler/brw_eu_validate.c:974:33: runtime error: shift exponent 64 is too large for 64-bit type 'long unsigned int' #0 0x561abb612ab3 in general_restrictions_on_region_parameters ../src/intel/compiler/brw_eu_validate.c:974 #1 0x561abb617574 in brw_validate_instructions ../src/intel/compiler/brw_eu_validate.c:1851 #2 0x561abb53bd31 in validate ../src/intel/compiler/test_eu_validate.cpp:106 #3 0x561abb555369 in validation_test_source_cannot_span_more_than_2_registers_Test::TestBody() ../src/intel/compiler/test_eu_validate.cpp:486 #4 0x561abb742651 in void testing::internal::HandleSehExceptionsInMethodIfSupported<testing::Test, void>(testing::Test*, void (testing::Test::*)(), char const*) ../src/gtest/src/gtest.cc:2402 #5 0x561abb72e64d in void testing::internal::HandleExceptionsInMethodIfSupported<testing::Test, void>(testing::Test*, void (testing::Test::*)(), char const*) ../src/gtest/src/gtest.cc:2438 #6 0x561abb6d5451 in testing::Test::Run() ../src/gtest/src/gtest.cc:2474 #7 0x561abb6d7b2a in testing::TestInfo::Run() ../src/gtest/src/gtest.cc:2656 #8 0x561abb6da2b8 in testing::TestCase::Run() ../src/gtest/src/gtest.cc:2774 #9 0x561abb6f5c92 in testing::internal::UnitTestImpl::RunAllTests() ../src/gtest/src/gtest.cc:4649 #10 0x561abb74626a in bool testing::internal::HandleSehExceptionsInMethodIfSupported<testing::internal::UnitTestImpl, bool>(testing::internal::UnitTestImpl*, bool (testing::internal::UnitTestImpl::*)(), char const*) ../src/gtest/src/gtest.cc:2402 #11 0x561abb732025 in bool testing::internal::HandleExceptionsInMethodIfSupported<testing::internal::UnitTestImpl, bool>(testing::internal::UnitTestImpl*, bool (testing::internal::UnitTestImpl::*)(), char const*) ../src/gtest/src/gtest.cc:2438 #12 0x561abb6ed2b4 in testing::UnitTest::Run() ../src/gtest/src/gtest.cc:4257 #13 0x561abb768b3b in RUN_ALL_TESTS() ../src/gtest/include/gtest/gtest.h:2233 #14 0x561abb7689fb in main ../src/gtest/src/gtest_main.cc:37 #15 0x7f525e5a9bba in __libc_start_main ../csu/libc-start.c:308 #16 0x561abb538ed9 in _start (/home/daenzer/src/mesa-git/mesa/build-amd64-sanitize/src/intel/compiler/eu_validate+0x1b8ed9) Reviewed-by: Adam Jackson <[email protected]>
* anv: fix error messageEric Engestrom2019-10-241-5/+2
| | | | | | | | | | | `strerror()` takes an `errno`, not the negative value returned by the `ioctl()`. Instead of fixing this as `"%s", strerror(errno)`, let's just use the `"%m"` shortcut for it. Fixes: 2b5f30b1d91b98ab27ba ("anv: implement VK_INTEL_performance_query") Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* anv: implement VK_INTEL_performance_queryLionel Landwerlin2019-10-239-18/+535
| | | | | | | | | | | | | | | | | | | | | v2: Introduce the appropriate pipe controls Properly deal with changes in metric sets (using execbuf parameter) Record marker at query end v3: Fill out PerfCntr1&2 v4: Introduce vkUninitializePerformanceApiINTEL v5: Use new execbuf extension mechanism v6: Fix comments in genX_query.c (Rafael) Use PIPE_CONTROL workarounds (Rafael) Refactor on the last kernel series update (Lionel) v7: Only I915_PERF_IOCTL_CONFIG when perf stream is already opened (Lionel) Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]>
* intel/perf: add mdapi writes for register perf countersLionel Landwerlin2019-10-231-0/+36
| | | | | | | Those are not part of the OA reports. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]>
* intel/genxml: add RPSTAT register for core frequencyLionel Landwerlin2019-10-238-0/+40
| | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]>
* intel/genxml: add generic perf counters registersLionel Landwerlin2019-10-234-0/+72
| | | | | | | | | | We have 2 of those we can configure to source programmable events. Those are not part of the OA reports. Configuration happens in i915 through the metric set selected by the application. On the Mesa side we'll just sample those and do a diff. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]>
* intel/perf: add support for querying kernel loaded configurationsLionel Landwerlin2019-10-232-27/+181
| | | | | | | We use this as a communication mechanism between MDAPI & Anv. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]>
* intel/perf: move registers to their own headerLionel Landwerlin2019-10-233-25/+55
| | | | | | | Will conflict with the genxml RPSTAT register. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]>
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