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* intel/isl: Add bounds-checking assertions for the format_info tableJason Ekstrand2018-06-071-8/+16
| | | | | | | | | | | We follow the same convention as isl_format_get_layout in having two assertions to ensure that only valid formats are passed in. We also check against the array size of the table because some valid formats such as CCS formats will may be past the end of the table. This fixes some potential out-of-bounds array access even in valid cases. Cc: [email protected] Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/isl: Add bounds-checking assertions in isl_format_get_layoutJason Ekstrand2018-06-072-12/+22
| | | | | | | | | | | | We add two assertions instead of one because the first assertion that format != ISL_FORMAT_UNSUPPORTED is more descriptive and checks for a real but unsupported enumerant while the second ensures that they don't pass in garbage values. We also update some other helpers to use isl_format_get_layout instead of using the table directly so that they get bounds checking too. Cc: [email protected] Reviewed-by: Lionel Landwerlin <[email protected]>
* anv: Set fence/semaphore types to NONE in impl_cleanupJason Ekstrand2018-06-071-13/+16
| | | | | | | | | | There were some places that were calling anv_semaphore_impl_cleanup and neither deleting the semaphore nor setting the type back to NONE. Just set it to NONE in impl_cleanup to avoid these issues. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106643 Fixes: 031f57eba "anv: Add a basic implementation of VK_KHX_external..." Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/blorp: Emit VF cache invalidates for 48-bit bugs with softpin.Kenneth Graunke2018-06-062-5/+22
| | | | | | | | | | | | | | | | | | commit 92f01fc5f914fd500497d0c3aed75f3ac8dc054d made i965 start emitting VF cache invalidates when the high bits of vertex buffers change. But we were not tracking vertex buffers emitted by BLORP. This was papered over by a mistake where I emitted VF cache invalidates all the time, which Chris fixed in commit 3ac5fbadfd8644d30fce9ff267cb811ad157996a. This patch adds a new hook which allows the driver to track addresses and request a VF cache invalidate as appropriate. v2: Make the driver do the PIPE_CONTROL so it can apply workarounds (caught by Jason Ekstrand). Rebase on anv bug fix. v3: Don't screw up the boolean (caught by Jason Ekstrand). Fixes: 92f01fc5f914 ("i965: Emit VF cache invalidates for 48-bit addressing bugs with softpin.") Reviewed-by: Jason Ekstrand <[email protected]>
* intel/blorp: Don't vertex fetch directly from clear valuesJason Ekstrand2018-06-061-44/+41
| | | | | | | | | | | | | | On gen8+, we have to VF cache flush whenever a vertex binding aliases a previous binding at the same index modulo 4GiB. We deal with this in Vulkan by ensuring that vertex buffers and the dynamic state (from which BLORP pulls its vertex buffers) are in the same 4GiB region of the address space. That doesn't work if we're reading clear colors with the VF unit. In order to work around this we switch to using MI commands to copy the clear value into the vertex buffer we allocate for the normal constant data. Cc: [email protected] Reviewed-by: Kenneth Graunke <[email protected]>
* intel/eu: Use a struct copy instead of a memcpyJason Ekstrand2018-06-051-1/+1
| | | | | | | | | The memcpy had the wrong size and this was causing crashes on 32-bit builds of the driver. Fixes: 6a9525bf6729a8 "intel/eu: Switch to a logical state stack" Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106830 Reviewed-by: Kenneth Graunke <[email protected]>
* intel/tools: add intel_sanitize_gpu to EXTRA_DISTScott D Phillips2018-06-051-0/+2
| | | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106778 Fixes: cc41603d6d ("intel/tools: new intel_sanitize_gpu tool") Reviewed-by: Dylan Baker <[email protected]>
* anv: intel: add softpin flag on imported BOsLionel Landwerlin2018-06-051-0/+2
| | | | | | | | | Looks like we forgot to update this bit of the driver for softpin. Fixes: 4affeba1e9eb42 ("anv: Soft-pin everything else") Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Tapani Pälli <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/eu: Switch to a logical state stackJason Ekstrand2018-06-043-126/+72
| | | | | | | | Instead of the state stack that's based on copying a dummy instruction around, we start using a logical stack of brw_insn_states. This uses a bit less memory and is way less conceptually bogus. Reviewed-by: Kenneth Graunke <[email protected]>
* intel/eu: Set flag [sub]register number differently for 3srcJason Ekstrand2018-06-041-3/+10
| | | | | | | | | | | Prior to gen8, the flag [sub]register number is in a different spot on 3src instructions than on other instructions. Starting with Broadwell, they made it consistent. This commit fixes bugs that occur when a conditional modifier gets propagated into a 3src instruction such as a MAD. Cc: [email protected] Reviewed-by: Kenneth Graunke <[email protected]>
* intel/eu: Copy fields manually in brw_next_insnJason Ekstrand2018-06-041-1/+94
| | | | | | | | Instead of doing a memcpy, this moves us to start with a blank instruction (memset to zero) and copy the fields over one at a time. Cc: [email protected] Reviewed-by: Kenneth Graunke <[email protected]>
* intel/eu: Add some brw_get_default_ helpersJason Ekstrand2018-06-044-55/+79
| | | | | | | | This is much cleaner than everything that wants a default value poking at the bits of p->current directly. Cc: [email protected] Reviewed-by: Kenneth Graunke <[email protected]>
* anv: Don't even bother processing relocs if we have softpinJason Ekstrand2018-06-011-3/+15
| | | | Reviewed-by: Scott D Phillips <[email protected]>
* anv: Refactor reloc handling in execbuf_add_boJason Ekstrand2018-06-011-36/+42
| | | | | | | This just separates the reloc list vs. BO set cases and lets us avoid an allocation if relocs->deps->entries == 0. Reviewed-by: Scott D Phillips <[email protected]>
* anv: Assert that the kernel leaves pinned BO addresses aloneJason Ekstrand2018-06-011-1/+4
| | | | Reviewed-by: Scott D Phillips <[email protected]>
* anv: Soft-pin everything elseScott D Phillips2018-06-013-1/+21
| | | | | | | | v2 (Jason Ekstrand): - Break up Scott's mega-patch Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Scott D Phillips <[email protected]>
* anv: Soft-pin batch buffersScott D Phillips2018-06-014-11/+30
| | | | | | Co-authored-by: Jason Ekstrand <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Scott D Phillips <[email protected]>
* anv/batch_chain: Simplify secondary batch return chainingJason Ekstrand2018-06-011-40/+36
| | | | | | | | | | | | | | | Previously, we did this weird thing where we left space and an empty relocation for use in a hypothetical MI_BATCH_BUFFER_START that would be added to the secondary later. Then, when it came time to chain it into the primary, we would back that out and emit an MI_BATCH_BUFFER_START. This worked well but it was always a bit hacky, fragile and ugly. This commit instead adds a helper for rewriting the MI_BATCH_BUFFER_START at the end of an anv_batch_bo and we use that helper for both batch bo list cloning and handling returns from secondaries. The new helper doesn't actually modify the batch in any way but instead just adjusts the relocation as needed. Reviewed-by: Scott D Phillips <[email protected]>
* anv/batch_chain: Call batch_bo_finish at the end of end_batch_bufferJason Ekstrand2018-06-011-6/+6
| | | | | | | | | | The only reason we were calling it in the middle was that one of the cases for figuring out the secondary command buffer execution type wanted batch_bo->length which gets set by batch_bo_finish. It's easy enough to recalculate and now batch_bo_finish is called in a sensible location. Reviewed-by: Scott D Phillips <[email protected]>
* anv: Soft-pin client-allocated memoryJason Ekstrand2018-06-011-0/+3
| | | | | | | | Now that we've done all that refactoring, addresses are now being directly written into surface states by ISL and BLORP whenever a BO is pinned so there's really nothing to do besides enable it. Reviewed-by: Scott D Phillips <[email protected]>
* anv/allocator: Support softpin in the BO cacheJason Ekstrand2018-06-011-1/+50
| | | | Reviewed-by: Scott D Phillips <[email protected]>
* anv/allocator: Set the BO flags in bo_cache_alloc/importJason Ekstrand2018-06-015-28/+60
| | | | | | | It's safer to set them there because we have the opportunity to properly handle combining flags if a BO is imported more than once. Reviewed-by: Scott D Phillips <[email protected]>
* anv: For pinned BOs, skip relocations, but track bo usageScott D Phillips2018-06-012-0/+66
| | | | | | | | | | | | | | | | | References to pinned BOs won't need to be relocated at a later point, so just write the final value of the reference into the bo directly. Add a `set` to the relocation lists for tracking dependencies that were previously tracked by relocations. When a batch is executed, we add the referenced pinned BOs to the exec list. v2: - visit bos from the dependency set in a deterministic order (Jason) v3: - compar => compare, drat (Jason) - Reworded commit message, provided by (Jordan) Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* anv: Use a separate pool for binding tables when soft pinningScott D Phillips2018-06-013-11/+53
| | | | | | | | | | | | | | | | | | | | | | Soft pinning lets us satisfy the binding table address requirements without using both sides of a growing state_pool. If you do use both sides of a state pool, then you need to read the state pool's center_bo_offset (with the device mutex held) to know the final offset of relocations that target the state pool bo. By having a separate pool for binding tables that only grows in the forward direction, the center_bo_offset is always 0 and relocations don't need an update pass to adjust relocations with the mutex held. v2: - don't introduce a separate state flag for separate binding tables (Jason) - replace bo and map accessors with a single binding_table_pool accessor (Jason) v3: - assert bt_block->offset >= 0 for the separate binding table (Jason) Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* anv: Soft-pin state poolsScott D Phillips2018-06-017-10/+34
| | | | | | | | | | | | | The state_pools reserve virtual address space of the full BLOCK_POOL_MEMFD_SIZE, but maintain the current behavior of growing from the middle. v2: - rename block_pool::offset to block_pool::start_address (Jason) - assign state pool start_address statically (Jason) v3: - remove unnecessary bo_flags tampering for the dynamic pool (Jason) Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965: Add ARB_fragment_shader_interlock support.Plamena Manolova2018-06-017-6/+34
| | | | | | | | | Adds suppport for ARB_fragment_shader_interlock. We achieve the interlock and fragment ordering by issuing a memory fence via sendc. Signed-off-by: Plamena Manolova <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* anv/blorp: Write relocated values into surface statesScott D Phillips2018-05-313-16/+22
| | | | | | | | v2 (Jason Ekstrand): - Split the blorp bit into it's own patch and re-order a bit - Use anv_address helpers Reviewed-by: Jason Ekstrand <[email protected]>
* anv: Use an address for each anv_image planeJason Ekstrand2018-05-315-35/+32
| | | | | | This is better than having BO and offset fields. Reviewed-by: Scott D Phillips <[email protected]>
* anv/cmd_buffer: Rework surface relocation helpersJason Ekstrand2018-05-311-25/+19
| | | | | | | | | This commit renames add_surface_state_reloc to add_surface_reloc and makes it takes an address. We also rename add_image_view_relocs to add_surface_state_relocs because it takes an anv_surface_state and doesn't really care about the image view anymore. Reviewed-by: Scott D Phillips <[email protected]>
* anv: Use an anv_address in anv_bufferJason Ekstrand2018-05-319-61/+34
| | | | Reviewed-by: Scott D Phillips <[email protected]>
* anv/cmd_buffer: Use anv_address for handling indirect parametersJason Ekstrand2018-05-311-44/+51
| | | | Reviewed-by: Scott D Phillips <[email protected]>
* anv: Use an anv_address in anv_buffer_viewJason Ekstrand2018-05-315-27/+36
| | | | | | | | Instead of storing a BO and offset separately, use an anv_address. This changes anv_fill_buffer_surface_state to use anv_address and we now call anv_address_physical and pass that into ISL. Reviewed-by: Scott D Phillips <[email protected]>
* anv: Use full anv_addresses in anv_surface_stateJason Ekstrand2018-05-313-51/+55
| | | | | | | | | | This refactors surface state filling to work entirely in terms of anv_addresses instead of offsets. This should make things simpler for when we go to soft-pin image buffers. Among other things, add_image_view_relocs now only cares about the addresses in the surface state and doesn't really need the image view anymore. Reviewed-by: Scott D Phillips <[email protected]>
* anv: Add some anv_address helpersJason Ekstrand2018-05-311-0/+24
| | | | Reviewed-by: Scott D Phillips <[email protected]>
* anv: Add vma_heap allocators in anv_deviceScott D Phillips2018-05-312-0/+144
| | | | | | | | | | | | | | | | | | | | | | | | | | | | These will be used to assign virtual addresses to soft pinned buffers in a later patch. Two allocators are added for separate 'low' and 'high' virtual memory areas. Another alternative would have been to add a double-sided allocator, which wasn't done here just because it didn't appear to give any code complexity advantages. v2 (Scott Phillips): - rename has_exec_softpin to use_softpin (Jason) - Only remove bottom one page and top 4 GiB from virt (Jason) - refer to comment in anv_allocator about state address + size overflowing 48 bits (Jason) - Mention hi/lo allocators vs double-sided allocator in commit message (Chris) - assign state pool memory ranges statically (Jason) v3 (Jason Ekstrand): - Use (LOW|HIGH)_HEAP_(MIN|MAX)_ADDRESS rather than (1 << 31) for determining which heap to use in anv_vma_free - Only return de-canonicalized addresses to the heap Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Scott D Phillips <[email protected]>
* intel/common: Add an address de-canonicalization helperJason Ekstrand2018-05-311-0/+12
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Scott D Phillips <[email protected]>
* intel/fs: Add explicit last_rt flag to fb writes orthogonal to eot.Francisco Jerez2018-05-294-5/+5
| | | | | | | | | | | | | | When using multiple RT write messages to the same RT such as for dual-source blending or all RT writes in SIMD32, we have to set the "Last Render Target Select" bit on all write messages that target the last RT but only set EOT on the last RT write in the shader. Special-casing for dual-source blend works today because that is the only case which requires multiple RT write messages per RT. When we start doing SIMD32, this will become much more common so we add a dedicated bit for it. Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* intel/fs: Replace the CINTERP opcode with a simple MOVFrancisco Jerez2018-05-295-12/+3
| | | | | | | | | | | | | The only reason it was it's own opcode was so that we could detect it and adjust the source register based on the payload setup. Now that we're using the ATTR file for FS inputs, there's no point in having a magic opcode for this. v2 (Jason Ekstrand): - Break the bit which removes the CINTERP opcode into its own patch Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* intel/fs: Use the ATTR file for FS inputsFrancisco Jerez2018-05-294-22/+30
| | | | | | | | | | | | This replaces the special magic opcodes which implicitly read inputs with explicit use of the ATTR file. v2 (Jason Ekstrand): - Break into multiple patches - Change the units of the FS ATTR to be in logical scalars Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* intel/fs: Rename a local variable so it doesn't shadow component()Francisco Jerez2018-05-291-4/+4
| | | | | | | | | v2 (Jason Ekstrand): - Break the refactor into its own patch Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* intel/eu: Remove brw_codegen::compressed_stack.Francisco Jerez2018-05-291-1/+0
| | | | | | Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* intel/fs: Use groups for SIMD16 LINTERP on gen11+Jason Ekstrand2018-05-291-4/+5
| | | | | | | | | | | This is better than compression control because it naturally extends to SIMD32. v2: - Push/pop instruction state around adjusted codegen (Ken) Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* intel/fs: Assert that the gen4-6 plane restrictions are followedJason Ekstrand2018-05-291-2/+8
| | | | | | | The fall-back does not work correctly in SIMD16 mode and the register allocator should ensure that we never hit this case anyway. Reviewed-by: Matt Turner <[email protected]>
* anv: move canonical_address calculation into a separate functionScott D Phillips2018-05-275-11/+47
| | | | | | | | | | | A later patch will make use of this in other places. Also, remove dependency on undefined behavior of left-shifting a signed value. v2: - move function into a separate header (Chris) v3: (by Ken) Add new header to the various build systems. Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/blorp: Support blits and clears on surfaces with offsetsJason Ekstrand2018-05-254-1/+37
| | | | | | | | | | | | | For certain EGLImage cases, we represent a single slice or LOD of an image with a byte offset to a tile and X/Y intratile offsets to the given slice. Most of i965 is fine with this but it breaks blorp. This is a terrible way to represent slices of a surface in EGL and we should stop some day but that's a very scary and thorny path. This gets blorp to start working with those surfaces and fixes some dEQP EGL test bugs. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106629 Cc: [email protected] Reviewed-by: Kenneth Graunke <[email protected]>
* intel/eu: Set EXECUTE_1 when setting the rounding mode in cr0Jason Ekstrand2018-05-221-0/+2
| | | | | Fixes: d6cd14f2131a5b "i965/fs: Define new shader opcode to..." Reviewed-by: Jose Maria Casanova Crespo <[email protected]>
* i965/glk: Add l3 banks count for 2x6 configurationAnuj Phogat2018-05-211-1/+1
| | | | | | | | | | | | 2x6 configuration with pci-id 0x3185 has same number of banks (2) as 3x6 configuration (pci-id 0x3184). Reported-by: Clayton Craft <[email protected]> Signed-off-by: Anuj Phogat <[email protected]> Tested-by: Clayton Craft <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Fixes: eb23be1d97da "i965: Add and initialize l3_banks field for gen7+" Cc: Francisco Jerez <[email protected]>
* android: enable VK_ANDROID_native_bufferTapani Pälli2018-05-211-3/+0
| | | | | | | | | | | | | | Patch changes entrypoints generator to not skip this extension even though it is set as disabled in the xml. We also need compilation flag VK_USE_PLATFORM_ANDROID_KHR to be enabled. It looks like this extension got disabled in commit 69f447553c. v2: just remove the whole 'supported' attrib check + remove vk_icd.h compilation fix (fix in VulkanHeaders instead) Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: isl: Move the MCS gen7+ assertion into ISLNanley Chery2018-05-181-0/+2
| | | | | | | This is useful for every user of ISL. Drop the comment along the way to match similar functions in ISL. Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/blorp: Add a NO_UPDATE_CLEAR_COLOR batch flagNanley Chery2018-05-172-2/+9
| | | | | | | | | Allow callers to handle updating the indirect clear color buffer themselves. This can reduce the number of clear color updates in the case where a caller performs multiple fast clears with the same clear color. Reviewed-by: Jason Ekstrand <[email protected]>
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