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* anv: add anv_ahw_usage_from_vk_usage helper functionTapani Pälli2018-12-193-0/+40
* anv/android: add GetAndroidHardwareBufferPropertiesANDROIDTapani Pälli2018-12-191-0/+119
* anv: add from/to helpers with android and vulkan formatsTapani Pälli2018-12-191-0/+50
* anv: make anv_get_image_format_features publicTapani Pälli2018-12-192-11/+16
* anv: refactor make_surface to use data from anv_imageTapani Pälli2018-12-192-37/+46
* anv: add create_flags as part of anv_imageTapani Pälli2018-12-192-0/+2
* anv: Bump the patch version to 96Jason Ekstrand2018-12-181-1/+1
* intel/compiler: More peephole_select for pre-Gen6Ian Romanick2018-12-171-2/+2
* nir/opt_peephole_select: Don't peephole_select expensive math instructionsIan Romanick2018-12-171-2/+2
* intel/compiler: More peephole selectIan Romanick2018-12-171-1/+14
* nir/opt_peephole_select: Don't try to remove flow control around indirect loadsIan Romanick2018-12-171-1/+12
* i965/vec4: Propagate conditional modifiers from more compares to other comparesIan Romanick2018-12-171-3/+100
* i965/fs: Eliminate unary op on operand of compare-with-zeroIan Romanick2018-12-172-17/+14
* i965/vec4/dce: Don't narrow the write mask if the flags are usedIan Romanick2018-12-174-10/+208
* i965/vec4: Silence unused parameter warnings in vec4 compiler testsIan Romanick2018-12-173-9/+9
* anv,radv: Re-enable VK_EXT_pci_bus_infoJason Ekstrand2018-12-171-1/+1
* nir: Add a bool to int32 lowering passJason Ekstrand2018-12-161-0/+2
* nir: Rename Boolean-related opcodes to include 32 in the nameJason Ekstrand2018-12-163-102/+102
* intel/genxml: Add register for object preemption.Rafael Antognolli2018-12-143-0/+24
* genxml: Consistently use a numeric "MOCS" fieldKenneth Graunke2018-12-1415-253/+170
* nir: Move intel's half-float image store lowering to to nir_format.h.Eric Anholt2018-12-131-8/+2
* Revert "intel: Simplify the half-float packing in image load/store lowering."Eric Anholt2018-12-131-2/+8
* i965: Enable nir_opt_idiv_const for 32 and 64-bit integersJason Ekstrand2018-12-131-1/+3
* i965/vec4: Implement nir_op_uadd_satJason Ekstrand2018-12-131-0/+6
* i965/fs: Implement nir_op_uadd_satIan Romanick2018-12-131-0/+5
* intel: Simplify the half-float packing in image load/store lowering.Eric Anholt2018-12-121-8/+2
* nir: Pull some of intel's image load/store format conversion to nir_format.hEric Anholt2018-12-121-18/+2
* intel/blorp: Assert that we don't re-layout a compressed surfaceJason Ekstrand2018-12-121-0/+3
* anv/pipeline: Set the correct binding count for compute shadersJason Ekstrand2018-12-121-2/+6
* intel/compiler: do not copy-propagate strided regions to ddx/ddy argumentsIago Toral Quiroga2018-12-121-0/+21
* anv: Advertise support for MinLod on Skylake+Jason Ekstrand2018-12-112-1/+2
* intel/fs: Support min_lod parameters on texture instructionsJason Ekstrand2018-12-114-2/+31
* intel/ir: Don't allow allocating zero registersJason Ekstrand2018-12-111-0/+1
* anv,radv: Disable VK_EXT_pci_bus_infoJason Ekstrand2018-12-111-1/+1
* i965/fs: Handle V/UV immediates in dump_instructions()Matt Turner2018-12-101-0/+5
* intel/compiler: Always print flag subregister numberSagar Ghuge2018-12-101-7/+6
* intel/compiler: Set swizzle to BRW_SWIZZLE_XXXX for scalar regionSagar Ghuge2018-12-101-1/+18
* intel/blorp: Expand blorp_address::offset to be 64 bits.Kenneth Graunke2018-12-071-1/+1
* nir: Make boolean conversions sized just like the othersJason Ekstrand2018-12-052-11/+17
* anv/query: flush render target before copying resultsLionel Landwerlin2018-12-055-0/+32
* anv: add unreachable() for VK_EXT_fragment_density_mapEric Engestrom2018-12-041-0/+3
* intel/tools: make sure the binary file is properly readAndrii Simiklit2018-12-041-3/+13
* intel/aubinator_error_decode: Get rid of warning for missing switch caseToni Lönnberg2018-12-041-0/+3
* mesa: Revert INTEL_fragment_shader_ordering supportMatt Turner2018-12-031-1/+0
* anv: flush pipeline before query result copiesLionel Landwerlin2018-11-291-5/+4
* intel/compiler: Use nir's info when checking uses_streams.Kenneth Graunke2018-11-281-1/+1
* intel/compiler: fix register allocation in opt_peephole_selIago Toral Quiroga2018-11-281-2/+1
* intel/compiler: fix indentation style in opt_algebraic()Iago Toral Quiroga2018-11-271-10/+10
* anv/icl: Set use full ways in L3CNTLREGAnuj Phogat2018-11-262-0/+2
* intel/icl: Set way_size_per_bank to 4Anuj Phogat2018-11-261-1/+2
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