summaryrefslogtreecommitdiffstats
path: root/src/intel
Commit message (Expand)AuthorAgeFilesLines
* intel: common: print out all dword with field spanning multiple dwordsLionel Landwerlin2017-11-011-4/+6
* intel: decoder: build sorted linked lists of fieldsLionel Landwerlin2017-11-012-25/+34
* intel: common: expose gen_spec fieldsLionel Landwerlin2017-11-012-13/+13
* intel/compiler: Add functions to get prog_data and prog_key sizes for a stageJordan Justen2017-10-312-0/+42
* intel/compiler: Add union types for prog_data and prog_key stagesJordan Justen2017-10-311-0/+22
* intel/compiler: Remove final_program_size from brw_compile_*Jordan Justen2017-10-3111-71/+40
* intel/compiler: add new field for storing program sizeCarl Worth2017-10-316-14/+35
* intel/isl: Disable some gen10 CCS_E formats for nowNanley Chery2017-10-311-0/+24
* intel/genxml: Fix decoding of groups with fields smaller than a DWord.Kenneth Graunke2017-10-302-10/+16
* intel: common: silence compiler warningLionel Landwerlin2017-10-301-1/+1
* i965: remove unused variableEric Engestrom2017-10-301-3/+0
* glsl: Remove ir_binop_greater and ir_binop_lequal expressionsIan Romanick2017-10-301-4/+0
* i965: fix blorp stage_prog_data->param leakTapani Pälli2017-10-301-1/+1
* i965: Delete brw_wm_prog_key::drawable_height.Kenneth Graunke2017-10-291-1/+0
* intel/compiler/gen9: Pixel shader header only workaroundTopi Pohjolainen2017-10-281-0/+29
* anv: Fix assert about source attrs.Kenneth Graunke2017-10-271-1/+1
* anv: Drop URB entry output read handling in 3DSTATE_XS.Kenneth Graunke2017-10-271-26/+0
* i965: Delete unused brw_vs_prog_data::nr_attributes field.Kenneth Graunke2017-10-272-2/+0
* intel/tools/disasm: correctly observe FILE *out parameterKevin Rogovin2017-10-261-2/+2
* intel/compiler: brw_validate_instructions to take const void* instead of void*Kevin Rogovin2017-10-262-2/+2
* anv/entrypoints: Dump useful data if mako throws an exceptionJason Ekstrand2017-10-251-5/+17
* intel/compiler: Call nir_lower_system_values in brw_preprocess_nirJason Ekstrand2017-10-252-2/+2
* anv/pipeline: Call nir_lower_system_valaues after brw_preprocess_nirJason Ekstrand2017-10-251-1/+2
* anv/pipeline: Drop nir_lower_clip_cull_distance_arraysJason Ekstrand2017-10-251-2/+0
* anv/pipeline: Dump shader immedately after spirv_to_nirJason Ekstrand2017-10-251-0/+15
* intel/eu: Use EXECUTE_1 for JMPIJason Ekstrand2017-10-252-2/+1
* i965/fs: Add brw_reg_type_from_bit_size utility methodAlejandro Piñeiro2017-10-251-5/+64
* i965/fs/nir: Use the nir_src_bit_size helperJason Ekstrand2017-10-251-9/+3
* intel/fs: Handle flag read/write aliasing in needs_src_copyJason Ekstrand2017-10-251-1/+3
* intel/nir: Zero local index const struct for valgrind & nir_serializeJordan Justen2017-10-251-0/+1
* meson: extract out variable for nir_algebraic.pyRob Clark2017-10-241-1/+1
* i965: Fix memmem compiler warnings.Eric Anholt2017-10-241-1/+2
* anv: don't assert on device init on CannonlakeLionel Landwerlin2017-10-211-2/+4
* anv: disable stencil pma fix on Gen > 9Lionel Landwerlin2017-10-211-0/+2
* blorp: enable R32G32B32X32 blorp ccs copiesLionel Landwerlin2017-10-211-0/+1
* i965/fs: Use align1 mode on ternary instructions on Gen10+Matt Turner2017-10-201-4/+8
* i965: Add align1 ternary instruction emission supportMatt Turner2017-10-201-55/+160
* i965: Add align1 ternary instruction disassembler supportMatt Turner2017-10-202-75/+288
* i965: Add align1 ternary instruction-word supportMatt Turner2017-10-201-0/+108
* i965: Add align1 ternary instruction support to conversion functionsMatt Turner2017-10-204-34/+101
* i965: Add align1 ternary instruction field encodingsMatt Turner2017-10-201-0/+35
* i965: Add functions to abstract access to 3src register typesMatt Turner2017-10-202-20/+23
* i965: Rename brw_inst's functions that access the 3src register typeMatt Turner2017-10-203-18/+18
* i965: Rename brw_inst 3src functions in preparation for align1Matt Turner2017-10-204-86/+92
* i965: Print subreg in units of type-size on ternary instructionsMatt Turner2017-10-201-5/+26
* i965: Add functions for brw_reg_type <-> hw 3src typeMatt Turner2017-10-202-0/+58
* i965: Move brw_reg_type_is_floating_point to brw_reg_type.hMatt Turner2017-10-202-13/+15
* nir: Get rid of nir_shader::stageJason Ekstrand2017-10-2011-37/+38
* i965/vec4: remove setting default LOD in the backendSamuel Iglesias Gonsálvez2017-10-202-21/+0
* i965/fs: remove setting default LOD in the backendSamuel Iglesias Gonsálvez2017-10-201-9/+0
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-21 09:55:56 +0000