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* intel/decoder: tools: Use engine for decoding batch instructionsToni Lönnberg2018-11-138-53/+69
| | | | | | | | | | | | | | | | The engine to which the batch was sent to is now set to the decoder context when decoding the batch. This is needed so that we can distinguish between instructions as the render and video pipe share some of the instruction opcodes. v2: The engine is now in the decoder context and the batch decoder uses a local function for finding the instruction for an engine. v3: Spec uses engine_mask now instead of engine, replaced engine class enums with the definitions from UAPI. v4: Fix up aubinator_viewer (Lionel) Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/decoder: tools: gen_engine to drm_i915_gem_engine_classToni Lönnberg2018-11-134-25/+19
| | | | | | | | | | Removed the gen_engine enum and changed the involved functions to use the drm_i915_gem_engine_class enum from UAPI instead. v3: Wrong engine was being used for blocks in video ring v4: Fixed aubinator_viewer.cpp Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/decoder: Engine parameter for instructionsToni Lönnberg2018-11-132-0/+31
| | | | | | | | | | | | | | | | | | | Preliminary work for adding handling of different pipes to gen_decoder. Each instruction needs to have a definition describing which engine it is meant for. If left undefined, by default, the instruction is defined for all engines. v2: Changed to use the engine class definitions from UAPI v3: Changed I915_ENGINE_CLASS_TO_MASK to use BITSET_BIT, change engine to engine_mask, added check for incorrect engine and added the possibility to define an instruction to multiple engines using the "|" as a delimiter in the engine attribute. v4: Fixed the memory leak. v5: Removed an unnecessary ralloc_free(). Reviewed-by: Lionel Landwerlin <[email protected]>
* anv/i965: make use of nir_link_constant_varyings()Timothy Arceri2018-11-131-0/+3
| | | | | | | | | | | | | | | | | | | shader-db results for SLK: total instructions in shared programs: 13106498 -> 13091573 (-0.11%) instructions in affected programs: 1186244 -> 1171319 (-1.26%) helped: 6186 HURT: 0 total cycles in shared programs: 332062633 -> 331961653 (-0.03%) cycles in affected programs: 8537165 -> 8436185 (-1.18%) helped: 5371 HURT: 862 LOST: 6 GAINED: 14 Reviewed-by: Jason Ekstrand <[email protected]>
* i965: add support for sampling from AYUVLionel Landwerlin2018-11-122-0/+2
| | | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Tapani Pälli <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* intel/fs: Prevent emission of IR instructions not aligned to their own ↵Francisco Jerez2018-11-091-3/+17
| | | | | | | | | | | | | | | | | execution size. This can occur during payload setup of SIMD-split send message instructions, which can lead to the emission of header setup instructions with a non-zero channel group and fixed SIMD width. Such instructions could end up using undefined channel enable signals except they don't care since they're always marked force_writemask_all. Not known to affect correctness of any workload at this point, but it would be trivial to back-port to stable if something comes up. Reported-by: Sagar Ghuge <[email protected]> Reviewed-by: Matt Turner <[email protected]> Tested-by: Sagar Ghuge <[email protected]>
* intel/aub_read: remove useless breaksLionel Landwerlin2018-11-091-6/+0
| | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* intel/compiler: fix node interference of simd16 instructionsIago Toral Quiroga2018-11-091-19/+17
| | | | | | | | | | | | | | | | | SIMD16 instructions need to have additional interferences to prevent source / destination hazards when the source and destination registers are off by one register. While we already have code to handle this, it was only running for SIMD16 dispatches, however, we can have SIDM16 instructions in a SIMD8 dispatch. An example of this are pull constant loads since commit b56fa830c6095, but there are more cases. This fixes a number of CTS test failures found in work-in-progress tests that were hitting this situation for 16-wide pull constants in a SIMD8 program. Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* intel/fs: Add an assert to optimize_frontfacing_ternaryJason Ekstrand2018-11-081-0/+3
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* anv: Use nir_src_is_const and friends in lowering codeJason Ekstrand2018-11-082-12/+9
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* intel/analyze_ubo_ranges: Use nir_src_is_const and friendsJason Ekstrand2018-11-081-8/+7
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* intel/vec4: Use the new nir_src_is_const and friendsJason Ekstrand2018-11-083-54/+46
| | | | | | | | | As of this commit, all uses of const sources either go through a nir_src_as_<type> helper which handles bit sizes correctly or else are accompanied by a nir_src_bit_size() == 32 assertion to assert that we have the size we think we have. Reviewed-by: Kenneth Graunke <[email protected]>
* intel/fs: Use the new nir_src_is_const and friendsJason Ekstrand2018-11-081-110/+87
| | | | | | | | | As of this commit, all uses of const sources either go through a nir_src_as_<type> helper which handles bit sizes correctly or else are accompanied by a nir_src_bit_size() == 32 assertion to assert that we have the size we think we have. Reviewed-by: Kenneth Graunke <[email protected]>
* intel/fs,vec4: Clean up a repeated pattern with SSBOsJason Ekstrand2018-11-084-166/+85
| | | | | | | | Everywhere we handle SSBO intrinsics, we have exactly the same pattern for computing the index so we may as well make a helper for it. We also add a get_nir_src_imm to vec4 and use it for SSBO offsets. Reviewed-by: Kenneth Graunke <[email protected]>
* intel/dump_gpu: add platform optionLionel Landwerlin2018-11-072-6/+29
| | | | | | | Got tired of remembering the PCI ids. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* intel/dump_gpu: move output option togetherLionel Landwerlin2018-11-071-5/+5
| | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* anv/android: mark gralloc allocated BOs as externalLionel Landwerlin2018-11-061-1/+1
| | | | | | | | | | Allocating through Gralloc implies buffers are going to be used outside the driver. We have special MOCS settings for external BOs and we probably want to use them here too. Signed-off-by: Lionel Landwerlin <[email protected]> Fixes: a1220e73116bad7 ("anv/android: Set the BO flags in bo_cache_import (v2)") Reviewed-by: Tapani Pälli <[email protected]>
* anv: stub internal android codeLionel Landwerlin2018-11-067-11/+80
| | | | | | | | | | | | | This reduces the amount of #ifdef ANDROID we'll have to have inside the driver. Potentially offering better coverage of the android extensions. v2: Move anv_android.h include before anv_entrypoints.h (Tapani) Fix autotools android build (Lionel) Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Tapani Pälli <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* intel/decoders: fix instruction base address parsingLionel Landwerlin2018-11-052-2/+2
| | | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Fixes: 00103db04ab879 ("intel: Fix decoding for partial STATE_BASE_ADDRESS updates.") Reviewed-by: Kenneth Graunke <[email protected]>
* intel/sanitize_gpu: add debug message on mmap failLionel Landwerlin2018-11-051-1/+3
| | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* intel/sanitize_gpu: deal with non page multiple buffer sizesLionel Landwerlin2018-11-051-4/+7
| | | | | | | | We can only map at page aligned offsets. We got that wrong with buffer size where (size % 4096) != 0 (anv has a WA buffer of 1024). Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* intel/sanitize_gpu: add help/gdb options to wrapperLionel Landwerlin2018-11-051-1/+54
| | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* intel/dump_gpu: add missing gdb optionLionel Landwerlin2018-11-051-0/+2
| | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* intel: Use a URB start offset of 0 for disabled stages.Kenneth Graunke2018-11-031-3/+9
| | | | | | | | | | | | | | | | | | | | | | | There are some cases where the VS is the only stage enabled, it uses the entire URB, and the URB is large enough that placing later stages after the VS exceeds the number of bits for "URB Starting Address". For example, on Icelake GT2, "varying-packing-simple mat2x4 array" from Piglit is getting a starting offset of 128 for the GS/HS/DS. But the field is only large enough to hold an offset of 127. i965 doesn't hit any genxml assertions because it's still using the old OUT_BATCH mechanism. 128 << GEN7_URB_STARTING_ADDRESS_SHIFT (57) == 0, with the extra bit falling off the end. So we place the disabled stage at the beginning of the URB (overlapping with push constants). This is likely okay since it's a zero size region (0 entries). It seems like the Vulkan driver might hit this assertion, however, and the situation seems harmless. To work around this, always place disabled stages at the start of the URB, so the last enabled stage can fill the remaining space without overflowing the field. Reviewed-by: Jordan Justen <[email protected]>
* anv/icl: Disable prefetching of sampler state entriesAnuj Phogat2018-11-021-9/+16
| | | | | | | | | | | WA_1606682166: Incorrect TDL's SSP address shift in SARB for 16:6 & 18:8 modes. Disable the Sampler state prefetch functionality in the SARB by programming 0xB000[30] to '1'. This is to be done at boot time and the feature must remain disabled permanently. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* anv/icl: Set Error Detection Behavior Control Bit in L3CNTLREGAnuj Phogat2018-11-012-0/+8
| | | | | | | | The default setting of this bit is not the desirable behavior. WA_1406697149 Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/tools: fix resource leakAndrii Simiklit2018-11-011-0/+10
| | | | | | | | | Some memory and file descriptors are not freed/closed. v2: fixed case where we skipped the 'aub' variable initialization Signed-off-by: Andrii Simiklit <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/tools: include stdarg.h in error2aubJonathan Gray2018-11-011-0/+1
| | | | | | | | | Include stdarg.h in error2aub.c otherwise it fails to build on OpenBSD due to not finding definitions for va_list va_start va_end. Signed-off-by: Jonathan Gray <[email protected]> Cc: [email protected] Reviewed-by: Lionel Landwerlin <[email protected]>
* configure: allow building with python3Emil Velikov2018-10-313-7/+7
| | | | | | | | | | | | | | | Pretty much all of the scripts are python2+3 compatible. Check and allow using python3, while adjusting the PYTHON2 refs. Note: - python3.4 is used as it's the earliest supported version - python2 chosen prior to python3 v2: use python2 by default Cc: Ilia Mirkin <[email protected]> Signed-off-by: Emil Velikov <[email protected]> Acked-by: Eric Engestrom <[email protected]>
* tools/imgui: disable all warningsEric Engestrom2018-10-311-1/+2
| | | | | | | | | This is an external project we have no control over, and will not be fixing (other than by sometimes pulling the latest sources), so warnings serve no purpose here. Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/compiler: Stop assuming the entrypoint is called "main"Jason Ekstrand2018-10-304-23/+5
| | | | | | | | | | | This isn't true for Vulkan so we have to whack it to "main" in anv which is silly. Instead of walking the list of functions and asserting that everything is named "main" and hoping there's only one function named "main", just use the nir_shader_get_entrypoint() helper which has better assertions anyway. Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* anv: Disable dual source blending when shader doesn't support it on gen8+Danylo Piliaiev2018-10-301-10/+36
| | | | | | | | | | | | | | | | | | | | | | | | | Dual source blending behaviour is undefined when shader doesn't have second color output. "If SRC1 is included in a src/dst blend factor and a DualSource RT Write message is not used, results are UNDEFINED. (This reflects the same restriction in DX APIs, where undefined results are produced if “o1” is not written by a PS – there are no default values defined)." Dismissing fragment in such situation leads to a hang on gen8+ if depth test in enabled. Since blending cannot be gracefully fixed in such case and the result is undefined - blending is simply disabled. v2 (Jason Ekstrand): - Apply the workaround to each individual entry - Emit a warning through debug_report Signed-off-by: Danylo Piliaiev <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* aub_viewer: show vertex buffer pitchEric Engestrom2018-10-301-1/+1
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* anv: Bump the advertised patch version to 90Jason Ekstrand2018-10-301-1/+1
| | | | Reviewed-by: Lionel Landwerlin <[email protected]>
* intel: tools: Add handling for video pipeToni Lönnberg2018-10-302-1/+30
| | | | | | | | Preliminary work for adding handling of different pipes to gen_decoder. We need to be able to distinguish between different pipes in order to decode the packets correctly due to opcode re-use. Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/decoder: Use 'DWord Length' and 'bias' fields for packet length.Toni Lönnberg2018-10-302-7/+25
| | | | | | | | Use the 'DWord Length' and 'bias' fields from the instruction definition to parse the packet length from the command stream when possible. The hardcoded mechanism is used whenever an instruction doesn't have this field. Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/batch-decoder: remove never-used functionEric Engestrom2018-10-302-42/+0
| | | | | | | | | This function was there when the file was introduced in commit 38f10d5a03542c60a589 "intel: tools: add aubinator viewer", but was never actually used. Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* anv: add missing meson build dependencyEric Engestrom2018-10-291-1/+1
| | | | | | | Fixes: e4538b93f5d5177318f2 "anv: Implement VK_KHR_driver_properties" Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Dylan Baker <[email protected]>
* anv: Use absolute timeouts in wait_for_bo_fencesJason Ekstrand2018-10-271-42/+30
| | | | | | | | | | | We were previously using relative timeouts and decrementing the user-provided timeout as we waited. Instead, this commit refactors things to use absolute timeouts throughout. This should fix a subtle bug in the waitAll case where we aren't decrementing the timeout after a successful GPU wait. Since pthread_cond_timedwait already takes an absolute timeout, it's also significantly simpler. Reviewed-by: Lionel Landwerlin <[email protected]>
* anv: Flag semaphore BOs as externalJason Ekstrand2018-10-271-2/+3
| | | | | | | | It probably doesn't actually break anything but it does cause some assertions in debug builds. Fixes: 7a89a0d9edae6 "anv: Use separate MOCS settings for external BOs" Reviewed-by: Lionel Landwerlin <[email protected]>
* anv: Improve the asserts in anv_buffer_get_rangeJason Ekstrand2018-10-271-1/+2
| | | | Reviewed-by: Lionel Landwerlin <[email protected]>
* Revert "anv/skylake: disable ForceThreadDispatchEnable"Jason Ekstrand2018-10-261-35/+7
| | | | | | | | | | This reverts commit 0fa9e6d7b304f6a8064ed78a4b9c557e1026e7e5. The real issue appears to have been that HiZ ops don't like having WM thread dispatch force-enabled. The previous commit fixes that problem so we can go back to using the ForceThreadDispatchEnable bit even on SKL+. Cc: [email protected] Reviewed-by: Kenneth Graunke <[email protected]>
* blorp: Emit a dummy 3DSTATE_WM prior to 3DSTATE_WM_HZ_OPJason Ekstrand2018-10-261-0/+9
| | | | | | Cc: [email protected] Suggested-by: Francisco Jerez <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* anv: Return VK_ERROR_DEVICE_LOST from anv_device_set_lostJason Ekstrand2018-10-264-45/+32
| | | | | | | This lets us get rid of a bunch of duplicated error messages. Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* anv/util: Split a vk_errorv helper out of vk_errorfJason Ekstrand2018-10-262-6/+25
| | | | | Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* intel/blorp: Define the clear value bounds for HiZ clearsNanley Chery2018-10-261-0/+14
| | | | | | | | | | | | | | | | Follow the restriction of making sure the clear value is between the min and max values defined in CC_VIEWPORT. Avoids a simulator warning for some piglit tests, one of them being: ./bin/depthstencil-render-miplevels 146 d=z32f_s8 Jason found this to fix incorrect clearing on SKL. Fixes: 09948151ab1d5184b4dd9052bb1f710fa1e00a7b ("intel/blorp: Add the BDW+ optimized HZ_OP sequence to BLORP") Reviewed-by: Jason Ekstrand <[email protected]> Tested-by: Jason Ekstrand <[email protected]>
* vulkan: drop always-true paramEric Engestrom2018-10-261-2/+0
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/nir: Use the OPT macro for more passesJason Ekstrand2018-10-261-3/+3
| | | | Reviewed-by: Ian Romanick <[email protected]>
* nir/builder: Add a nir_imm_true/false helpersJason Ekstrand2018-10-261-1/+1
| | | | | Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* nir/validate: Print when the validation failedJason Ekstrand2018-10-262-5/+5
| | | | | Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
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