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* anv: Allocate block pool BOs from the cacheJason Ekstrand2019-10-312-48/+34
* anv/tests: Initialize the BO cache and device mutexJason Ekstrand2019-10-316-0/+8
* anv/tests: Zero-initialize instancesJason Ekstrand2019-10-316-6/+14
* anv: Choose BO flags internally in anv_block_poolJason Ekstrand2019-10-319-76/+70
* anv: Rework the internal BO allocation APIJason Ekstrand2019-10-316-102/+217
* anv: Use anv_block_pool_foreach_bo in get_bo_from_poolJason Ekstrand2019-10-311-6/+5
* anv: Rework anv_block_pool_expand_rangeJason Ekstrand2019-10-312-103/+76
* anv: Fix a potential BO handle leakJason Ekstrand2019-10-311-1/+3
* anv: Handle state pool relocations using "wrapper" BOsJason Ekstrand2019-10-313-14/+56
* anv: Replace ANV_BO_EXTERNAL with anv_bo::is_externalJason Ekstrand2019-10-316-20/+22
* anv: Inline anv_block_pool_get_boJason Ekstrand2019-10-311-27/+13
* anv: Declare the bo in the anv_block_pool_foreach_bo loopJason Ekstrand2019-10-313-3/+2
* anv: Stop storing the GEM handle in anv_reloc_list_addJason Ekstrand2019-10-311-1/+1
* anv: Fix a relocation race conditionJason Ekstrand2019-10-314-12/+25
* anv: Use a util_sparse_array for the GEM handle -> BO mapJason Ekstrand2019-10-312-90/+36
* anv: Move refcount to anv_boJason Ekstrand2019-10-312-61/+50
* intel/perf: fix Android buildLionel Landwerlin2019-10-311-1/+2
* anv: Remove _mesa_locale_init/fini calls.Bas Nieuwenhuizen2019-10-311-3/+0
* intel/perf: add TGL supportLionel Landwerlin2019-10-314-0/+8611
* intel/compiler: Report the number of non-spill/fill SEND messages on vec4 tooIan Romanick2019-10-301-5/+35
* intel/dev: set default num_eu_per_subslice on gen12Lionel Landwerlin2019-10-301-1/+2
* intel/eu/validate/gen12: Add TGL to eu_validate tests.Jordan Justen2019-10-301-0/+9
* intel/dev: Add preliminary device info for TigerlakeJordan Justen2019-10-301-0/+49
* intel/dump_gpu: handle context create extended ioctlLionel Landwerlin2019-10-301-0/+15
* anv: Add Tile Cache Flush for Unified Cache.Rafael Antognolli2019-10-303-1/+45
* blorp: Add Tile Cache Flush for Unified Cache.Rafael Antognolli2019-10-301-0/+3
* intel/genxml: Add gen12 tile cache flush bitJordan Justen2019-10-301-0/+1
* anv: Align fast clear color state buffer to a page.Rafael Antognolli2019-10-301-0/+9
* intel/compiler: Add instruction compaction support on Gen12Matt Turner2019-10-302-184/+868
* intel/compiler: Make separate src0/src1 index tablesMatt Turner2019-10-301-11/+18
* intel/compiler: Inline get_src_index()Matt Turner2019-10-301-26/+15
* intel/compiler: Restructure instruction compaction in preparation for Gen12Matt Turner2019-10-301-20/+28
* intel/compiler: Remove unreachable() from brw_reg_type.cMatt Turner2019-10-301-3/+3
* anv: Avoid emitting UBO surface states that won't be usedJason Ekstrand2019-10-301-1/+12
* intel/vec4: Set brw_stage_prog_data::has_ubo_pullJason Ekstrand2019-10-301-0/+2
* intel/isl: Allow stencil buffer to support compression on Gen12+Sagar Ghuge2019-10-291-2/+3
* intel/blorp: Set stencil resolve enable bitSagar Ghuge2019-10-291-4/+17
* intel: Track stencil aux usage on Gen12+Sagar Ghuge2019-10-293-0/+9
* intel/blorp: Add helper function for stencil buffer resolveSagar Ghuge2019-10-292-0/+34
* intel/blorp: Assign correct view while clearing depth stencilSagar Ghuge2019-10-291-1/+1
* genxml/gen12: Add Stencil Buffer Resolve Enable bitSagar Ghuge2019-10-291-0/+1
* anv: Reduce the minimum number of relocationsJason Ekstrand2019-10-291-1/+1
* anv: Delay allocation of relocation listsJason Ekstrand2019-10-291-67/+71
* anv: Implement new way for setting streamout buffers.Plamena Manolova2019-10-293-0/+19
* genxml: Add 3DSTATE_SO_BUFFER_INDEX_* instructionsPlamena Manolova2019-10-291-0/+47
* anv: Set depthBounds to true in anv_GetPhysicalDeviceFeatures.Plamena Manolova2019-10-291-1/+1
* genxml: Change 3DSTATE_DEPTH_BOUNDS bias.Plamena Manolova2019-10-291-1/+1
* intel/perf: update ICL configurationsLionel Landwerlin2019-10-291-59/+28
* anv: Fix output of INTEL_DEBUG=bat for chained batchesCaio Marcelo de Oliveira Filho2019-10-281-1/+1
* loader: default to iris for all future PCI IDsEric Engestrom2019-10-282-0/+3
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