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* intel/isl: Move isl_calc_array_pitch_el_rows higher upJason Ekstrand2017-06-011-117/+117
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/isl: Remove the device parameter from isl_tiling_get_infoJason Ekstrand2017-06-014-30/+16
| | | | | | | | | We were only using it for validating that we don't use Ys/Yf on gen8 and earlier. Removing it from isl_tiling_get_info lets us remove it from a bunch of other things that had no business needing a hardware generation. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Drop duplicate shadow variable.Kenneth Graunke2017-06-011-1/+0
| | | | | | We already initialized this at the top of the function. Trivial.
* genxml: Make 3DSTATE_CONSTANT_BODY on Gen7+ use arrays.Kenneth Graunke2017-06-015-36/+28
| | | | | | This will let us initialize the constant buffers with loops. Reviewed-by: Lionel Landwerlin <[email protected]>
* genxml: Fix decoder to print the array element on field members.Kenneth Graunke2017-06-011-3/+9
| | | | | | | | | | | | | | | | | | | | | | | | | Previously we'd print things like: 0xfffbb568: 0x00010000 : Dword 1 ReadLength: 0 ReadLength: 1 0xfffbb568: 0x00000001 : Dword 1 ReadLength: 1 ReadLength: 0 instead of the more obvious: 0xfffbb568: 0x00010000 : Dword 1 ReadLength[0]: 0 ReadLength[1]: 1 0xfffbb568: 0x00000001 : Dword 1 ReadLength[2]: 1 ReadLength[3]: 0 (Yes, the ralloc context here is bogus - the decoder leaks just about everything. We need to use proper ralloc contexts someday...) Acked-by: Lionel Landwerlin <[email protected]>
* genxml: Fix decoding of array groups.Kenneth Graunke2017-06-011-1/+1
| | | | | | | | | | | | | | | | | | | If you had a group as the first element of a struct, i.e. <struct name="3DSTATE_CONSTANT_BODY" length="10"> <group count="4" start="0" size="16"> <field name="ReadLength" start="0" end="15" type="uint"/> </group> ... </struct> we would get a group_offset of 0, causing create_field() to think the field wasn't in a group, and fail to offset forward for successive array elements. So we'd mark all the array elements as offset 0. Using ctx->group->elem_size is a better check for "are we in a group?". Acked-by: Lionel Landwerlin <[email protected]>
* genxml: Fix decoder for groups with multiple fields.Kenneth Graunke2017-06-011-4/+2
| | | | | | | | | | | | | | | | | If you have something like: <group count="0" start="96" size="32"> <field name="Entry_0" start="0" end="15" type="GATHER_CONSTANT_ENTRY"/> <field name="Entry_1" start="16" end="31" type="GATHER_CONSTANT_ENTRY"/> </group> We would reset ctx->group_count to 0 after processing the first field, so the second would not have a group count. This is largely untested, as the only groups with multiple fields are packets we don't emit in Mesa. Found by inspection. Acked-by: Lionel Landwerlin <[email protected]>
* genxml: Fix parsing of address fields in groups.Kenneth Graunke2017-06-011-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | For example, <group count="4" start="64" size="64"> <field name="Pointer" start="5" end="63" type="address"/> </group> used to generate: const uint64_t v2_address = __gen_combine_address(data, &dw[2], values->Pointer, 0); ... const uint64_t v4_address = __gen_combine_address(data, &dw[4], values->Pointer, 0); ... but now generates code with proper subscripts: const uint64_t v2_address = __gen_combine_address(data, &dw[2], values->Pointer[0], 0); ... const uint64_t v4_address = __gen_combine_address(data, &dw[4], values->Pointer[1], 0); ... Reviewed-by: Lionel Landwerlin <[email protected]>
* i965: Move SOL PSIZ hacks from draw time to link time.Kenneth Graunke2017-06-011-12/+1
| | | | | | | | | We can just update the gl_transform_feedback_info fields at link time to make the VUE header fields have the right location and component. Then we don't need to handle them specially at draw time, which is expensive. Reviewed-by: Rafael Antognolli <[email protected]>
* anv: Port over CACHE_MODE_1 optimization fix enables from brw.Kenneth Graunke2017-05-301-0/+13
| | | | | | | | | Ben and I haven't observed these to help anything, but they enable hardware optimizations for particular cases. It's probably best to enable them ahead of time, before we run into such a case. Reviewed-by: Plamena Manolova <[email protected]> Acked-by: Jason Ekstrand <[email protected]>
* genxml: Add Gen9 CACHE_MODE_1 definitons.Kenneth Graunke2017-05-301-0/+30
| | | | | | | | | These were already in gen8.xml but not gen9.xml. There are a few new fields and a couple that have changed. These are all documented in the Skylake PRM, Volume 2c Command Reference: Registers, Part 1. Reviewed-by: Plamena Manolova <[email protected]> Acked-by: Jason Ekstrand <[email protected]>
* genxml: Make a SCISSOR_RECT structure on Gen4-5.Kenneth Graunke2017-05-293-12/+24
| | | | | | | | | | | | | Gen6+ support multiple scissor rectangles, and define a SCISSOR_RECT structure containing their dimensions. On Gen4-5, those same fields exist in SF_VIEWPORT. This patch extracts the SF_VIEWPORT fields into a SCISSOR_RECT structure. Although not a named concept on Gen4-5, it works just as well, and gives us a consistent SCISSOR_RECT structure across all generations, making it easier to reuse code. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Ignore INTEL_SCALAR_* debug variables on Gen10+.Kenneth Graunke2017-05-291-10/+16
| | | | | | | | | | | Scalar mode has been default since Broadwell, and vector mode is getting increasingly unmaintained. There are a few things that don't even fully work in vector mode on Skylake, but we've never cared because nobody uses it. There's no point in porting it forward to new platforms. So, just ignore the debug options to force it on. Reviewed-by: Jason Ekstrand <[email protected]>
* anv: automake: list shared libraries after the static onesEmil Velikov2017-05-291-16/+15
| | | | | | | | | | The compiler can discard the shared ones from the link chain, since there is no user (the static libraries) before it on the command line. Cc: [email protected] Reported-by: Laurent Carlier <[email protected]> Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Eduardo Lima Mitev <[email protected]>
* i965: Use BLORP for color clears on gen4-5Jason Ekstrand2017-05-261-0/+4
| | | | | | | | We don't support replicated data clears yet. Those take a bit more work and enabling replicated data clears in its own commit is probably better for bisectibility anyway. Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/blorp: Assert that no one tries to blit combined depth stencilJason Ekstrand2017-05-261-0/+6
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Add blorp support for gen4-5Jason Ekstrand2017-05-264-12/+95
| | | | | | | | | | Due to complications with things such as URB setup on gen4-5, it's easier to keep gen4 support in blorp completely internal to i965. This makes things a bit awkward because that means there's a file in i965 that includes blorp_priv.h but it's either that or have a file in blorp that includes brw_context.h. Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/blorp: Set additional brw_wm_prog_key fields on gen4-5Jason Ekstrand2017-05-262-2/+9
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/blorp: Add support for gen4-5 SF programsJason Ekstrand2017-05-266-3/+85
| | | | | | | | As part of enabling support for SF programs, we plumb the SF URB size through to emit_urb_config. For now, it's always zero but, on gen4, it may be something larger. Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/blorp: Make convert_to_single_slice available outside blorp_blitJason Ekstrand2017-05-262-8/+11
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/blorp: Use designated initializers to set up VERTEX_ELEMENTSJason Ekstrand2017-05-261-32/+43
| | | | | | | | We also add a slot variable and use it as an iterator. This will make it much easier to conditionally put something between the header and the vertex position. Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/blorp: Rename emit_viewport_state to emit_cc_viewportJason Ekstrand2017-05-261-3/+3
| | | | | | | The real point of this packet is that it sets up CC_VIEWPORT so that name is a bit better. Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/blorp: Make the common genX_blorp_exec code gen4-safeJason Ekstrand2017-05-261-8/+36
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/blorp: Re-arrange blorp_genX_exec.hJason Ekstrand2017-05-261-229/+229
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/blorp: Don't use ffma directlyJason Ekstrand2017-05-261-1/+1
| | | | | | | It isn't supported prior to gen6 and, on gen6+, NIR will fuse the fmul and fadd into an ffma automatically for us anyway. Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/blorp: Delete isl_to_gen_ds_surfypeJason Ekstrand2017-05-261-19/+0
| | | | | | It's no longer used. Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/blorp: Pull the pipeline bits of blorp_exec into a helperJason Ekstrand2017-05-261-25/+31
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/blorp/blit: Add support for normalized coordinatesJason Ekstrand2017-05-262-5/+28
| | | | | | | Gen5 and earlier can't do non-normalized coordinates so we need to compensate in the shader. Fortunately, it's pretty easy plumb through. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Move clip program compilation to the compilerJason Ekstrand2017-05-269-0/+2347
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Move SF compilation to the compilerJason Ekstrand2017-05-264-0/+932
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/compiler: Make brw_disasm take const assemblyJason Ekstrand2017-05-263-15/+15
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/decoder: Handle the BLT ring in gen_group_get_lengthJason Ekstrand2017-05-261-0/+4
| | | | Reviewed-by: Jordan Justen <[email protected]>
* intel/decoder: Handle gen4 VF_STATISTICS and PIPELINE_SELECTJason Ekstrand2017-05-261-2/+7
| | | | | | | These need special handling because they have no "DWord Length" parameter and they have an unusual bias of 1. Reviewed-by: Jordan Justen <[email protected]>
* intel/genxml: Rename 3DSTATE_AA_LINE_PARAMS on gen5Jason Ekstrand2017-05-261-1/+1
| | | | | | All of the other gens use "PARAMETERS". Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/genxml: Use the right subtype for VF_STATISTICS on gen4Jason Ekstrand2017-05-261-1/+1
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/genxml: Iron Lake doesn't support non-normalized sampler coordinatesJason Ekstrand2017-05-261-1/+0
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/genxml: Add SAMPLER_STATE to gen 4.5Jason Ekstrand2017-05-261-0/+63
| | | | | | Somehow this got missed. Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/genxml: Rename the CC_VIEWPORT pointer on gen4-5Jason Ekstrand2017-05-263-3/+3
| | | | | | | It isn't a pointer to "color calc state", that's the packet it's in. It's a pointer to the CC viewport state. Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/genxml: Sampler state is a pointer on gen4-5Jason Ekstrand2017-05-263-9/+9
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/genxml: Suffix KSP0 fields on Iron LakeJason Ekstrand2017-05-261-5/+5
| | | | | | | | | Iron Lake introduced the multiple KSP thing and so you have KSP0-3. However, the genxml didn't have an index on the first "Kernel Start Pointer" or "GRF Register Count". Add one to match gen6+. While we're here, we drop the brackets from the other "GRF Register Count" fields. Reviewed-by: Matt Turner <[email protected]>
* intel/genxml: Make a bunch of things offsets on gen4-5Jason Ekstrand2017-05-263-15/+15
| | | | | | | | | Most things on gen4-5 are addresses because we don't have dynamic state base address and we don't have instruction state base on gen4. However, whoever converted things to addresses got a little over-excited and converted too much. Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/isl: Add gen4_filter_tilingJason Ekstrand2017-05-263-2/+57
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/isl: Add support for setting component write disablesJason Ekstrand2017-05-262-0/+26
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/isl: Add support for gen4 cube maps to get_image_offset_saJason Ekstrand2017-05-261-5/+18
| | | | | | | Gen4 cube maps are a 2-D surface with ISL_DIM_LAYOUT_GEN4_3D which is a bit weird but accurate none the less. Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/isl: Don't request space for stencil/hiz packets unless neededJason Ekstrand2017-05-261-7/+6
| | | | | | | On Iron Lake, the packets exist but we never emit them so there's no need for us to ask the driver to make batch space for them. Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/blorp: Move the gen7 stencil format workaround to blorp_blitJason Ekstrand2017-05-262-5/+9
| | | | | | | | It's not needed for blorp_copy because it already overrides formats. It's also not needed for blorp_clear because it clears stencil as stencil. Reviewed-by: Topi Pohjolainen <[email protected]>
* aubinator: report error on unknown device idLionel Landwerlin2017-05-241-1/+1
| | | | | | | | | Since we're going to stop aubinator without a valid device id, better report an error. This also silences a Coverity warning. CID: 1405004 Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]>
* aubinator: be consistent on exit codeLionel Landwerlin2017-05-241-5/+5
| | | | | | | | We're using both exit(1) & exit(EXIT_FAILURE), settle for one, same for success. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]>
* aubinator: fix double freeLionel Landwerlin2017-05-241-1/+1
| | | | | | | | | 1;4601;0c Free previously allocated filename outside the for loop. CID: 1405014 Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]>
* anv: Require vertex buffers to come from a 32-bit heapJason Ekstrand2017-05-231-0/+12
| | | | | Reviewed-by: Nanley Chery <[email protected]> Cc: "17.1" <[email protected]>
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