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* anv/blorp: Remove 3D subresource transition workaroundNanley Chery2017-06-261-4/+4
* anv/cmd_buffer: Adjust the image view reloc functionNanley Chery2017-06-261-20/+25
* anv/cmd_buffer: Adjust layout transition aspect checkingNanley Chery2017-06-261-5/+3
* anv: Add and use color auxiliary buffer helpersNanley Chery2017-06-262-0/+32
* intel/isl: Only create a CCS buffer if the image supports renderingNanley Chery2017-06-261-1/+1
* intel/isl: Limit CCS to one level and layer on gen7Nanley Chery2017-06-261-2/+7
* intel/blorp: Check for layer fast-clear restrictionNanley Chery2017-06-261-0/+5
* intel/blorp: Assert levels and layers are in rangeNanley Chery2017-06-262-4/+7
* anv: use Mesa's u_atomic.h headerEric Engestrom2017-06-261-2/+3
* anv/cnl: Don't write to Cache Mode Register 1 on gen10+Anuj Phogat2017-06-231-3/+1
* genxml: fix gen5 sampler border color state.Rafael Antognolli2017-06-221-20/+20
* aubinator: Dump sampler state pointers on gen6 too.Rafael Antognolli2017-06-221-0/+11
* anv: Fix -Wswitch in anv_layout_to_aux_usage()Chad Versace2017-06-221-0/+3
* i965/CFL: Add PCI Ids for Coffee Lake.Anusha Srivatsa2017-06-222-0/+27
* intel: Enable vulkan build for gen10Anuj Phogat2017-06-221-0/+4
* anv/cnl: Generate and use gen10 functionsAnuj Phogat2017-06-224-1/+13
* anv/cnl: Don't set FloatBlendOptimizationEnable{Mask}Anuj Phogat2017-06-221-3/+6
* anv/cnl: Use GENX(xx) in place of GEN9_xxAnuj Phogat2017-06-221-8/+8
* anv/cnl: Add #defines for MOCS and genX(x)Anuj Phogat2017-06-221-0/+14
* intel/genxml: Add Gen10 CACHE_MODE_1 definitionsAnuj Phogat2017-06-221-0/+18
* intel/genxml: Rename StartInstanceLocation to StartingInstanceLocationAnuj Phogat2017-06-221-1/+1
* intel/genxml: Rename IndirectStatePointer to BorderColorPointerAnuj Phogat2017-06-221-1/+1
* intel/genxml: Combine DataDWord{0, 1} fields in to ImmediateData fieldAnuj Phogat2017-06-221-2/+1
* intel/genxml: Add INSTDONE registers in gen10Anuj Phogat2017-06-221-0/+115
* intel/genxml: Add better support for MI_MATH in gen10Anuj Phogat2017-06-221-4/+65
* anv: FORMAT_FEATURE_TRANSFER_SRC/DST_BIT_KHR not used with VkFormatProperties...Andres Gomez2017-06-221-5/+0
* intel/genxml: Use the same naming convention for Floating Point Mode.Rafael Antognolli2017-06-211-2/+2
* intel/genxml: Normalize URB Data field in WM_STATE.Rafael Antognolli2017-06-213-3/+3
* intel/genxml: Rename field on WM_STATE to match gen6+.Rafael Antognolli2017-06-213-3/+3
* intel/genxml: Normalize fields on WM_STATE.Rafael Antognolli2017-06-212-4/+4
* intel/genxml: Add missing field to CLIP_STATE.Rafael Antognolli2017-06-212-0/+5
* intel/genxml: Fix type of UserClipFlags ClipTest Enable Bitmask.Rafael Antognolli2017-06-213-3/+3
* intel/genxml: Add missing fields to CLIP_STATE on gen4-5.Rafael Antognolli2017-06-212-0/+2
* intel/genxml: Normalize GS_STATE.Rafael Antognolli2017-06-211-1/+1
* intel: compiler/i965: fix is_broxton checksLionel Landwerlin2017-06-205-6/+9
* i965/cnl: Add l3 configuration for CannonlakeBen Widawsky2017-06-201-1/+20
* i965: Add a variable for way size per bank in get_l3_way_size()Anuj Phogat2017-06-201-5/+4
* i965: Fix broxton 2x6 l3 configAnuj Phogat2017-06-201-0/+16
* intel/blorp: Apply source offset in the TEX caseIan Romanick2017-06-201-0/+3
* intel/blorp: Apply Gen4 coord. normalization after cubemap sizes are adjustedIan Romanick2017-06-201-9/+11
* intel/blorp: Set needs_(dst|src)_offset for Gen4 cubemapsJason Ekstrand2017-06-201-2/+6
* intel: common: add number of thread per euLionel Landwerlin2017-06-192-2/+28
* intel: common: express timestamps units in frequencyLionel Landwerlin2017-06-193-12/+14
* intel: common: add flag to identify platforms by nameLionel Landwerlin2017-06-192-6/+24
* anv: Fix L3 cache programming on Bay TrailJonas Kulla2017-06-191-1/+1
* intel/isl/gen6: Allow arrayed stencilTopi Pohjolainen2017-06-171-1/+0
* genxml: The viewport state offset is actually an address.Rafael Antognolli2017-06-161-1/+1
* genxml: Rename fields to match gen6+.Rafael Antognolli2017-06-163-3/+3
* genxml: Rename SF_STATE field to match gen6+.Rafael Antognolli2017-06-163-9/+9
* intel/isl: Add the maximum surface size limitAnuj Phogat2017-06-161-0/+22
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