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* anv: Implement VK_EXT_conditional_rendering for gen 7.5+Danylo Piliaiev2019-01-187-14/+265
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conditional rendering affects next functions: - vkCmdDraw, vkCmdDrawIndexed, vkCmdDrawIndirect, vkCmdDrawIndexedIndirect - vkCmdDrawIndirectCountKHR, vkCmdDrawIndexedIndirectCountKHR - vkCmdDispatch, vkCmdDispatchIndirect, vkCmdDispatchBase - vkCmdClearAttachments Value from conditional buffer is cached into designated register, MI_PREDICATE is emitted every time conditional rendering is enabled and command requires it. v2: by Jason Ekstrand - Use vk_find_struct_const instead of manually looping - Move draw count loading to prepare function - Zero the top 32-bits of MI_ALU_REG15 v3: Apply pipeline flush before accessing conditional buffer (The issue was found by Samuel Iglesias) v4: - Remove support of Haswell due to possible hardware bug - Made TMP_REG_PREDICATE and TMP_REG_DRAW_COUNT defines to define registers in one place. v5: thanks to Jason Ekstrand and Lionel Landwerlin - Workaround the fact that MI_PREDICATE_RESULT is not accessible on Haswell by manually calculating MI_PREDICATE_RESULT and re-emitting MI_PREDICATE when necessary. v6: suggested by Lionel Landwerlin - Instead of calculating the result of predicate once - re-emit MI_PREDICATE to make it easier to investigate error states. v7: suggested by Jason - Make anv_pipe_invalidate_bits_for_access_flag add CS_STALL if VK_ACCESS_CONDITIONAL_RENDERING_READ_BIT is set. v8: suggested by Lionel - Precompute conditional predicate's result to support secondary command buffers. - Make prepare_for_draw_count_predicate more readable. Signed-off-by: Danylo Piliaiev <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* anv: Implement VK_KHR_draw_indirect_count for gen 7+Danylo Piliaiev2019-01-182-0/+148
| | | | | | | | | | | | | | | v2: by Jason Ekstrand - Move out of the draw loop population of registers which aren't changed in it. - Remove dependency on ALU registers. - Clarify usage of PIPE_CONTROL - Without usage of ALU registers patch works for gen7+ v3: set pending_pipe_bits |= ANV_PIPE_RENDER_TARGET_WRITES Signed-off-by: Danylo Piliaiev <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* anv: Re-sort the extensions listJason Ekstrand2019-01-181-6/+6
| | | | | | I like to keep things in good order so that you can find them. Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/fs: Don't touch accumulator destination while applying regioning ↵Jason Ekstrand2019-01-181-1/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | alignment rule In some shaders, you can end up with a stride in the source of a SHADER_OPCODE_MULH. One way this can happen is if the MULH is acting on the top bits of a 64-bit value due to 64-bit integer lowering. In this case, the compiler will produce something like this: mul(8) acc0<1>UD g5<8,4,2>UD 0x0004UW { align1 1Q }; mach(8) g6<1>UD g5<8,4,2>UD 0x00000004UD { align1 1Q AccWrEnable }; The new region fixup pass looks at the MUL and sees a strided source and unstrided destination and determines that the sequence is illegal. It then attempts to fix the illegal stride by replacing the destination of the MUL with a temporary and emitting a MOV into the accumulator: mul(8) g9<2>UD g5<8,4,2>UD 0x0004UW { align1 1Q }; mov(8) acc0<1>UD g9<8,4,2>UD { align1 1Q }; mach(8) g6<1>UD g5<8,4,2>UD 0x00000004UD { align1 1Q AccWrEnable }; Unfortunately, this new sequence isn't correct because MOV accesses the accumulator with a different precision to MUL and, instead of filling the bottom 32 bits with the source and zeroing the top 32 bits, it leaves the top 32 (or maybe 31) bits alone and full of garbage. When the MACH comes along and tries to complete the multiplication, the result is correct in the bottom 32 bits (which we throw away) and garbage in the top 32 bits which are actually returned by MACH. This commit does two things: First, it adds an assert to ensure that we don't try to rewrite accumulator destinations of MUL instructions so we can avoid this precision issue. Second, it modifies required_dst_byte_stride to require a tightly packed stride so that we fix up the sources instead and the actual code which gets emitted is this: mov(8) g9<1>UD g5<8,4,2>UD { align1 1Q }; mul(8) acc0<1>UD g9<8,8,1>UD 0x0004UW { align1 1Q }; mach(8) g6<1>UD g5<8,4,2>UD 0x00000004UD { align1 1Q AccWrEnable }; Fixes: efa4e4bc5fc "intel/fs: Introduce regioning lowering pass" Reviewed-by: Francisco Jerez <[email protected]>
* intel/eu: Stop overriding exec sizes in send_indirect_messageJason Ekstrand2019-01-181-3/+0
| | | | | | | | For a long time, we based exec sizes on destination register widths. We've not been doing that since 1ca3a9442760b6f7 but a few remnants accidentally remained. Reviewed-by: Anuj Phogat <[email protected]>
* anv/tests: Adding test for the state_pool padding.Rafael Antognolli2019-01-172-1/+75
| | | | | | | Add a test that checks that we can use the extra space allocated for padding while allocating larger anv_states. Reviewed-by: Jason Ekstrand <[email protected]>
* anv/allocator: Add support for non-userptr.Rafael Antognolli2019-01-171-46/+71
| | | | | | | | | | | | | If softpin is supported, create new BOs for the required size and add the respective BO maps. The other main change of this commit is that anv_block_pool_map() now returns the map for the BO that the given offset is part of. So there's no block_pool->map access anymore (when softpin is used. v3: - set fd to -1 on softpin case (Jason) Reviewed-by: Jason Ekstrand <[email protected]>
* anv: Remove state flush.Rafael Antognolli2019-01-1710-51/+2
| | | | | | | We have all the state buffers snooped, so we don't need to clflush everything anymore. Reviewed-by: Jason Ekstrand <[email protected]>
* anv/allocator: Enable snooping on block pool and anv_bo_pool BOs.Rafael Antognolli2019-01-171-10/+16
| | | | | | | | | | | | | | | | | | We are not going to use userptr for anv block pool BOs anymore. However, so far we have been relying on the fact that userptr BOs are snooped on non-llc platforms. Let's make sure that the block pool BOs are still snooped, and we can also remove the clflush'ing that we do on all state buffers. And since we plan to remove the flushes, set the anv_bo_pool BOs to cached (snooped on non-LLC platforms) too. For LLC platforms, they are all cached by default, so this becomes a no-op. v5: - Add snooping to anv_bo_pool BOs too (Jason). - Remove anv_gem_set_domain. Reviewed-by: Jason Ekstrand <[email protected]>
* anv/allocator: Add padding information.Rafael Antognolli2019-01-173-10/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It's possible that we still have some space left in the block pool, but we try to allocate a state larger than that state. This means such state would start somewhere within the range of the old block_pool, and end after that range, within the range of the new size. That's fine when we use userptr, since the memory in the block pool is CPU mapped continuously. However, by the end of this series, we will have the block_pool split into different BOs, with different CPU mapping ranges that are not necessarily continuous. So we must avoid such case of a given state being part of two different BOs in the block pool. This commit solves the issue by detecting that we are growing the block_pool even though we are not at the end of the range. If that happens, we don't use the space left at the end of the old size, and consider it as "padding" that can't be used in the allocation. We update the size requested from the block pool to take the padding into account, and return the offset after the padding, which happens to be at the start of the new address range. Additionally, we return the amount of padding we used, so the caller knows that this happens and can return that padding back into a list of free states, that can be reused later. This way we hopefully don't waste any space, but also avoid having a state split between two different BOs. v3: - Calculate offset + padding at anv_block_pool_alloc_new (Jason). v4: - Remove extra "leftover". Reviewed-by: Jason Ekstrand <[email protected]>
* anv/allocator: Rework chunk return to the state pool.Rafael Antognolli2019-01-171-23/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit tries to rework the code that split and returns chunks back to the state pool, while still keeping the same logic. The original code would get a chunk larger than we need and split it into pool->block_size. Then it would return all but the first one, and would split that first one into alloc_size chunks. Then it would keep the first one (for the allocation), and return the others back to the pool. The new anv_state_pool_return_chunk() function will take a chunk (with the alloc_size part removed), and a small_size hint. It then splits that chunk into pool->block_size'd chunks, and if there's some space still left, split that into small_size chunks. small_size in this case is the same size as alloc_size. The idea is to keep the same logic, but make it in a way we can reuse it to return other chunks to the pool when we are growing the buffer. v2: - Include Jason's suggestions to the algorithm that returns chunks. - Update comments. v3: - Disallow returning 0 blocks (Jason). - fix min_size in the loop (Jason). - remove temporary variables (Jason) v4: - return_chunk() should never return blocks larger than pool->block_size. Reviewed-by: Jason Ekstrand <[email protected]>
* anv: Remove some asserts.Rafael Antognolli2019-01-171-3/+0
| | | | | | | They won't be true anymore once we add support for multiple BOs with non-userptr. Reviewed-by: Jason Ekstrand <[email protected]>
* anv: Validate the list of BOs from the block pool.Rafael Antognolli2019-01-171-5/+49
| | | | | | | | | | | | | | | | | | | We now have multiple BOs in the block pool, but sometimes we still reference only the first one in some instructions, and use relative offsets in others. So we must be sure to add all the BOs from the block pool to the validation list when submitting commands. v2: - Don't add block pool BOs to the dependency list right before execbuf (Jason) - Call anv_execbuf_add_bo() to each BO in the block pools (Jason) - Use anv_execbuf_add_bo_set() to add surface state dependencies to execbuf. v3: - Add comment to the non-softpin case (Jason). Reviewed-by: Jason Ekstrand <[email protected]>
* anv: Split code to add BO dependencies to execbuf.Rafael Antognolli2019-01-171-23/+39
| | | | | | | | | This part of the anv_execbuf_add_bo() code is totally independent of the BO being added. Let's split it out, so we can reuse it later. v3: rename to anv_execbuf_add_bo_set (Jason). Reviewed-by: Jason Ekstrand <[email protected]>
* anv/allocator: Add support for a list of BOs in block pool.Rafael Antognolli2019-01-172-11/+59
| | | | | | | | | | | | | | | | | | | So far we use only one BO (the last one created) in the block pool. When we switch to not use the userptr API, we will need multiple BOs. So add code now to store multiple BOs in the block pool. This has several implications, the main one being that we can't use pool->map as before. For that reason we update the getter to find which BO a given offset is part of, and return the respective map. v3: - Simplify anv_block_pool_map (Jason). - Use fixed size array for anv_bo's (Jason) v4: - Respect the order (item, container) in anv_block_pool_foreach_bo (Jason). Reviewed-by: Jason Ekstrand <[email protected]>
* anv: Update usage of block_pool->bo.Rafael Antognolli2019-01-177-31/+36
| | | | | | | | | | | Change block_pool->bo to be a pointer, and update its usage everywhere. This makes it simpler to switch it later to a list of BOs. v3: - Use a static "bos" field in the struct, instead of malloc'ing it. This will be later changed to a fixed length array of BOs. Reviewed-by: Jason Ekstrand <[email protected]>
* anv/allocator: Remove pool->map.Rafael Antognolli2019-01-173-19/+7
| | | | | | | | After switching to using anv_state_table, there are very few places left still using pool->map directly. We want to avoid that because it won't be always the right map once we split it into multiple BOs. Reviewed-by: Jason Ekstrand <[email protected]>
* anv/allocator: Rename anv_free_list2 to anv_free_list.Rafael Antognolli2019-01-172-31/+30
| | | | | | Now that we removed the original anv_free_list, we can now use its name. Reviewed-by: Jason Ekstrand <[email protected]>
* anv/allocator: Remove anv_free_list.Rafael Antognolli2019-01-172-66/+0
| | | | | | | The next commit already renames anv_free_list2 -> anv_free_list since the old one is gone. Reviewed-by: Jason Ekstrand <[email protected]>
* anv/allocator: Use anv_state_table on back_alloc too.Rafael Antognolli2019-01-172-15/+22
| | | | Reviewed-by: Jason Ekstrand <[email protected]>
* anv/allocator: Use anv_state_table on anv_state_pool_alloc.Rafael Antognolli2019-01-172-35/+48
| | | | | | | | | | Use anv_state_pool_return_blocks() to return blocks to the pool, instead of manually pushing them. v3: - return blocks from the end of the chunk (Jason). Reviewed-by: Jason Ekstrand <[email protected]>
* anv/allocator: Add helper to push states back to the state table.Rafael Antognolli2019-01-172-0/+35
| | | | | | | | | | | | | | The use of anv_state_table_add() combined with anv_state_table_push(), specially when adding a bunch of states to the table, is very verbose. So we add this helper that makes things easier to digest. We also already add the anv_state_table member in this commit, so things can compile properly, even though it's not used. v2: assert that the states are always aligned to their size (Jason) v3: Add "table" member to anv_state_pool in this commit. Reviewed-by: Jason Ekstrand <[email protected]>
* anv/allocator: Add getter for anv_block_pool.Rafael Antognolli2019-01-174-5/+18
| | | | | | | | | | We will need the anv_block_pool_map to find the map relative to some BO that is not at the start of the block pool. v2: just return a pointer instead of a struct (Jason) v4: Update comment (Jason) Reviewed-by: Jason Ekstrand <[email protected]>
* anv/allocator: Add anv_state_table.Rafael Antognolli2019-01-172-2/+283
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a structure to hold anv_states. This table will initially be used to recycle anv_states, instead of relying on a linked list implemented in GPU memory. Later it could be used so that all anv_states just point to the content of this struct, instead of making copies of anv_states everywhere. One has to call anv_state_table_add(), which returns an index for the state in the table, and then get a pointer to such index, and finally fill in the rest of the struct. TODO: 1) There's a lot of common code between this table backing store memory and the anv_block_pool buffer, due to how we grow it. I think it's possible to refactory this and reuse code on both places. 2) Add unit tests. v3: - Rename state table memfd (Jason) - Return VK_ERROR_OUT_OF_HOST_MEMORY on more places (Jason) - anv_state_table_grow returns VkResult (Jason) - Rename variables to be more informative (Jason) - Return errors on state table grow. - Rename anv_state_table_push/pop to anv_free_list_push2/pop2 This will be renamed again to remove the trailing "2" later. v4: - Remove exit(-1) from anv_state_table (Jason). - Use uint32_t "next" field in anv_free_entry (Jason). Reviewed-by: Jason Ekstrand <[email protected]>
* anv/tests: Fix block_pool_no_free test.Rafael Antognolli2019-01-171-14/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There were 2 problems with this test. First it was comparing highest, which was -1, with an uint32_t. So the current value would never be higher than that, and the assert would always be false. It just never reached this point because of the next problem. It was always looking for the highest value of each thread and storing it in thread_max. So a test case like this wouldn't work: [Thread]: [Blocks] [0]: [0, 32, 64, 96] [1]: [128, 160, 192, 224] [2]: [256, 288, 320, 352] Not only that would skip values and iterate only over thread number 2, instead of walking through all of them, but thread_max was also initialized to -1. And then compared to unsigned blocks[i][next[i]. We fix that by getting the smallest value of each thread, and checking if it is lower than thread_min, which is initialized to INT32_MAX. And then we end up walking through all the blocks of all threads. We also change "blocks" to be int32_t instead of uint32_t, since in some places (alloc_blocks) it was already referenced as int32_t, and that fixes the comparison to -1. v2: - keep highest initialized to -1, and change blocks to be int32_t. Reviewed-by: Jason Ekstrand <[email protected]>
* anv: fix invalid binding table index computationLionel Landwerlin2019-01-171-4/+2
| | | | | | | | The ++ operator strikes again. Fixes: f92c5bc8f3f517 ("anv/device: fix maximum number of images supported") Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* anv/device: fix maximum number of images supportedIago Toral Quiroga2019-01-174-13/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We had defined MAX_IMAGES as 8, which we used to size the array for image push constant data. The comment there stated that this was for gen8, but anv_nir_apply_pipeline_layout runs for all gens and writes that array, asserting that we don't exceed that number of images, which imposes a limit of MAX_IMAGES on all gens. Furthermore, despite this, we are exposing up to 64 images per shader stage on all gens, gen8 included. This patch lowers the number of images we expose in gen8 to 8 and keeps 64 images for gen9+ while making sure that only pre-SKL gens use push constant space to handle images. v2: - <= instead of < in the assert (Eric, Lionel) - Change the way the assertion is written (Eric) v3: - Revert the way the assertion is written to the form it had in v1, the version in v2 was not equivalent and was incorrect. (Lionel) v4: - gen9+ doesn't need push constants for images at all (Jason) Cc: [email protected] Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> (v3)
* anv: do not advertise AHW support if extension not enabledTapani Pälli2019-01-171-6/+15
| | | | | | | | | | | | | | | | Fixes following failing vk-gl-cts cases on Linux desktop: dEQP-VK.api.external.memory.android_hardware_buffer.suballocated.buffer.info dEQP-VK.api.external.memory.android_hardware_buffer.suballocated.image.info dEQP-VK.api.external.memory.android_hardware_buffer.dedicated.image.info dEQP-VK.api.external.memory.android_hardware_buffer.dedicated.buffer.info Fixes: 517103abf1c "anv/android: add ahardwarebuffer external memory properties" Reported-by: Juan A. Suarez <[email protected]> Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Juan A. Suarez <[email protected]>
* src/intel: use new hash table and set creation helpersCaio Marcelo de Oliveira Filho2019-01-143-8/+4
| | | | | | | | | Replace calls to create hash tables and sets that use _mesa_hash_pointer/_mesa_key_pointer_equal with the helpers _mesa_pointer_hash_table_create() and _mesa_pointer_set_create(). Reviewed-by: Jason Ekstrand <[email protected]> Acked-by: Eric Engestrom <[email protected]>
* anv: Implement VK_KHR_depth_stencil_resolveJason Ekstrand2019-01-145-1/+204
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* anv: Move resolve_subpass to genX_cmd_buffer.cJason Ekstrand2019-01-143-70/+59
| | | | | We may have to do transitions around certain kinds of resolves so it helps to have it genX code.
* anv/blorp: Refactor MSAA resolves into an exportable helper functionJason Ekstrand2019-01-142-132/+107
| | | | | | This function is modeled after the aux_op functions except that it has a lot more parameters because it deals with two images as well as source and destination regions.
* anv: Rename has_resolve to has_color_resolveJason Ekstrand2019-01-143-5/+5
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* intel/blorp: Add two more filter modesJason Ekstrand2019-01-142-12/+52
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* anv/pipeline_cache: free NIR shader cacheIago Toral Quiroga2019-01-141-0/+7
| | | | | Fixes: f6aa9f718516 'anv/pipeline_cache: Add support for caching NIR' Reviewed-by: Lionel Landwerlin <[email protected]>
* i965: Drop mark_surface_used mechanism.Kenneth Graunke2019-01-137-100/+0
| | | | | | | | | | | | | | | | | | | | | The original idea was that the backend compiler could eliminate surfaces, so we would have it mark which ones are actually used, then shrink the binding table accordingly. Unfortunately, it's a pretty blunt mechanism - it can only prune things from the end, not the middle - since we decide the layout before we even start the backend compiler, and only limit the size. It also basically gives up if it sees indirect array access. Besides, we do the vast majority of our surface elimination in NIR anyway, not the backend - and I don't see that trend changing any time soon. Vulkan abandoned this plan a long time ago, and I don't use it in Iris, but it's still been kicking around in i965. I hacked shader-db to print the binding table size in bytes, and observed no changes with this patch. So, this code appears to do nothing useful. Acked-by: Jason Ekstrand <[email protected]>
* intel/nir: Call nir_opt_deref in brw_nir_optimizeJason Ekstrand2019-01-121-0/+1
| | | | | | | It's an optimization so we should probably be calling it in the optimization loop. Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/peephole_ffma: Fix swizzle propagationJason Ekstrand2019-01-111-4/+7
| | | | | | | | | | | | | | | The num_components value passed into get_mul_for_src is used to only compose the parts of the swizzle that we know will be used so we don't compose invalid swizzle components. However, we had a bug where we passed the number of components of the add all the way through. For the given source, we need the number of components read from that source. In the case where we have a narrow add, say 2 components, that is sourced from a chain of wider instructions, we may not compose all the swizzles. All we really need to do is pass through the right number of components at each level. Fixes: 2231cf0ba3a "nir: Fix output swizzle in get_mul_for_src" Reviewed-by: Ian Romanick <[email protected]>
* anv/pipeline_cache: fix incorrect guards for NIR cacheIago Toral Quiroga2019-01-111-2/+3
| | | | | Fixes: f6aa9f718516 'anv/pipeline_cache: Add support for caching NIR' Reviewed-by: Lionel Landwerlin <[email protected]>
* blorp: Pass the batch to lookup/upload_shader instead of contextKenneth Graunke2019-01-106-31/+40
| | | | | | | | | This will allow drivers to pin shader buffers if necessary. i965 and anv do not need to do this today, but iris will. Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* blorp: Add blorp_get_surface_address to the driver interface.Kenneth Graunke2019-01-102-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, BLORP expects drivers to provide two functions for dealing with buffers: blorp_emit_reloc and blorp_surface_reloc. Both record a relocation and combine the BO address and offset into a full 64-bit address. Traditionally, blorp_surface_reloc has written that combined address to an implicitly-known buffer where surface states are stored. (In contrast, blorp_emit_reloc returns the value.) The upcoming Iris driver stores surface states in multiple buffers, which makes it impossible for blorp_surface_reloc to write the combined address - it only takes an offset, not the actual buffer to write to. This commit adds a third function, blorp_get_surface_address, which combines and returns an address, which is then passed to ISL's surface state fill functions. Softpin-only drivers can return a real address here and skip writing it in blorp_surface_reloc. Relocation-based drivers are have options. They can simply return 0 from the new function, and continue writing the address from blorp_surface_reloc. Or, they can return a presumed address from blorp_get_surface_address, and have other relocation processing write the real value later. For now, i965 and anv simply return 0. Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* anv/pipeline: Cache the pre-lowered NIRJason Ekstrand2019-01-101-10/+39
| | | | | | | | | | | | | | | | This adds a second level of caching for the pre-lowered NIR that's only based off of the shader module, entrypoint and specialization constants. This is enough for spirv_to_nir as well as our first round of lowering and optimization. Caching at this level should allow for faster shader recompiles due to state changes. The NIR caching does not get serialized to disk via either the VkPipelineCache serialization mechanism or the transparent on-disk cache. We could but it's usually not that expensive to fall back to SPIR-V for the odd cache miss especially if it only happens once for several misses and it simplifies the cache. Reviewed-by: Lionel Landwerlin <[email protected]>
* anv/pipeline_cache: Add support for caching NIRJason Ekstrand2019-01-102-0/+118
| | | | Reviewed-by: Lionel Landwerlin <[email protected]>
* anv/pipeline: Hash shader modules and spec constants separatelyJason Ekstrand2019-01-101-15/+39
| | | | | | | The stuff hashed by anv_pipeline_hash_shader is exactly the inputs to anv_shader_compile_to_nir so it can be used for NIR caching. Reviewed-by: Lionel Landwerlin <[email protected]>
* anv/pipeline: Move wpos and input attachment lowering to lower_nirJason Ekstrand2019-01-101-11/+8
| | | | | | | This lets us make anv_pipeline_compile_to_nir take a device instead of a pipeline. Reviewed-by: Lionel Landwerlin <[email protected]>
* anv/pipeline: Constant fold after apply_pipeline_layoutJason Ekstrand2019-01-102-12/+5
| | | | | | | | | | | | Thanks to the new NIR load_descriptor intrinsic added by the UBO/SSBO lowering series, we weren't getting UBO pushing because the UBO range detection pass couldn't see the constants it needed. This fixes that problem with a quick round of constant folding. Because we're folding we no longer need to go out of our way to generate constants when we lower the vulkan_resource_index intrinsic and we can make it a bit simpler. Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/isl: move tiled_memcpy static libs from i965 to islTapani Pälli2019-01-1010-5/+1353
| | | | | | | | | | | | | | Patch moves intel_tiled_memcpy[_sse41] libraries to isl, renames some functions and types and makes the required build system changes for meson, automake and Android. No functional changes are introduced. v2: code cleanups, move isl_get_memcpy_type to i965 (Jason) v3: move isl_mem_copy_fn to priv header, cleanups (Jason, Dylan) Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Dylan Baker <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965: Compile fp64 software routines and lower double-opsMatt Turner2019-01-091-22/+70
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* intel/compiler: Heap-allocate temporary storageMatt Turner2019-01-091-3/+5
| | | | | | | | Shaders containing software implementations of double-precision operations can be very large such that we cannot stack-allocate an array of grf_count*16. Reviewed-by: Kenneth Graunke <[email protected]>
* intel/compiler: Expand size of the 'nr' fieldMatt Turner2019-01-091-4/+3
| | | | | | | | | | | Shaders containing software implementations of double-precision operations can be very large such that we have more the 2^16 virtual registers during optimization. Move the 'nr' field to the union containing the immediate storage and expand it to 32-bits. Reviewed-by: Kenneth Graunke <[email protected]>
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