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* intel: common: express timestamps units in frequencyLionel Landwerlin2017-06-193-12/+14
| | | | | | | | | | | | | | Rather than storing the period as a double that looses some precision. Also fixes the Gen9LP timestamp frequency which is no 19200123 but 19200000 as pointed by Ville : https://lists.freedesktop.org/archives/intel-gfx/2017-April/125126.html Finally add the Cannonlake timestamp frequency. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel: common: add flag to identify platforms by nameLionel Landwerlin2017-06-192-6/+24
| | | | | | | | The perf infrastructure needs to identify specific platforms, not just generations. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* anv: Fix L3 cache programming on Bay TrailJonas Kulla2017-06-191-1/+1
| | | | | | | | | | | Valid values for URBAllocation start at 32, so substract that before programming the register. This was missed when porting from the GL driver. Cc: "17.1" <[email protected]> Reviewed-by: Francisco Jerez <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/isl/gen6: Allow arrayed stencilTopi Pohjolainen2017-06-171-1/+0
| | | | | | | | Nothing prevents arrayed stencil surfaces even though hardware doesn't support mipmapping. Reviewed-by: Nanley Chery <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* genxml: The viewport state offset is actually an address.Rafael Antognolli2017-06-161-1/+1
| | | | | | | This fixes code generation on gen45. Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* genxml: Rename fields to match gen6+.Rafael Antognolli2017-06-163-3/+3
| | | | | | | "Anti-aliasing Enable" to "Anti-Aliasing Enable". Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* genxml: Rename SF_STATE field to match gen6+.Rafael Antognolli2017-06-163-9/+9
| | | | | | | | | Rename "Use Point Width State" to "Point Width Source". It accepts the same values and has the same meaning as gen6+, so lets keep them with the same name to simplify the code. Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/isl: Add the maximum surface size limitAnuj Phogat2017-06-161-0/+22
| | | | | | | | V2: Use 2^31 bytes (2GB) surface size limit on pre-gen9 and 2^38 bytes for gen9+. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Nanley Chery <[email protected]>
* intel/isl: Use uint64_t to store total surface sizeAnuj Phogat2017-06-162-2/+3
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Nanley Chery <[email protected]>
* intel/blorp: Work around Sandy Bridge occlusion query issueJason Ekstrand2017-06-141-0/+10
| | | | Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* intel/isl: Properly set SeparateStencilBufferEnable on gen5-6Jason Ekstrand2017-06-141-3/+10
| | | | | | | On gen5-6, SeparateStencilBufferEnable and HierarchicalDepthBufferEnable come hand in hand and we have to set either both or neither. Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* genxml: Fix Gen4-5 SF_STATE "Line Width" fixed point type.Kenneth Graunke2017-06-143-3/+3
| | | | | | It's a U3.1. It became a U3.7 on Sandybridge. Reviewed-by: Rafael Antognolli <[email protected]>
* i965/cnl: Add a preliminary device for CannonlakeBen Widawsky2017-06-091-0/+46
| | | | | | | | | | | | | | | | v2 (Anuj): Rebased on master and updated pci ids Remove redundant initialization of max_wm_threads to 64 * 12. For gen9+ max_wm_threads are initialized in gen_get_device_info(). v3 (Anuj): Move the patch to end of series. Remove unused gt1, gt2, gt3 functions. Remove l3_banks variable. Variable is now available on master. Signed-off-by: Anuj Phogat <[email protected]> Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* anv: Don't advertise support on anything above gen9Jason Ekstrand2017-06-091-1/+1
| | | | | | | This will prevent the driver from even trying to work on Cannon Lake until we get actual support added. Reviewed-by: Anuj Phogat <[email protected]>
* i965/cnl: Enable CCS_E and RT support for few formatsAnuj Phogat2017-06-091-9/+9
| | | | | | Suggested-by: Jason Ekstrand <[email protected]> Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/cnl: Reformat surface_format_info table to accomodate gen10+Anuj Phogat2017-06-091-263/+263
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Acked-by: Jason Ekstrand <[email protected]>
* i965/cnl: Make URB {VS, GS, HS, DS} sizes non multiple of 3Anuj Phogat2017-06-094-4/+33
| | | | | | | | | | v1: By Ben Widawsky <[email protected]> v2: v1 had an assert only for VS. Add the restriction for GS, HS and DS as well and make sure the allocated sizes are not multiple of 3. v3: Move the entry_size checks in to compiler code (Ken) Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/cnl: Handle gen10 in switch cases across the driverAnuj Phogat2017-06-094-0/+13
| | | | | | | | | V2: Start using gen10 functions isl_gen10*(), gen10_blorp_exec() gen10_init_atoms() (Jason) Remove Vulkan changes. Do them later in a separate patch. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/cnl: Update few assertionsAnuj Phogat2017-06-091-1/+1
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/cnl: Add cnl bits in aubinatorAnuj Phogat2017-06-091-3/+5
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/cnl: Wire up android Mesa build files for gen10Anuj Phogat2017-06-093-0/+46
| | | | | | | | Signed-off-by: Anuj Phogat <[email protected]> Acked-by: Jason Ekstrand <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Mauro Rossi <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* i965/cnl: Wire up Mesa build files for gen10Anuj Phogat2017-06-093-3/+18
| | | | | | | | V2: Remove isl_gen10.c and isl_gen10.h Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* intel/genxml: Update genx_bits for gen10+Anuj Phogat2017-06-091-4/+2
| | | | | | | | | | | This commit adds a gen10 case to the switch statement and drops some unneeded code for handling gen numbers which doesn't work on gen10 and above. V2: Drop "z = float(z)" and the "z *= 10" lines Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/cnl: Add gen10 specific function declarationsAnuj Phogat2017-06-091-0/+12
| | | | | | | | | These declarations will help the code start compiling once we wire up the makefiles for gen10. Later patches will start using these functions for gen10. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/cnl: Include gen10_pack.hAnuj Phogat2017-06-091-0/+2
| | | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Nanley Chery <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/cnl: Define genX(x) and GENX(x) for gen10Anuj Phogat2017-06-091-0/+3
| | | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Nanley Chery <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/genxml: Add gen10.xmlJason Ekstrand2017-06-091-0/+3562
| | | | | | | | | | | | | | V2(Anuj): Add default value for length of 3DPRIMITIVE command Add values for 'Attribute Active Component Format' Rename few fields to match gen9.xml V3 (Ander Conselvan de Oliveira) Add gen10 alias for MOCS Make 3DSTATE_CONSTANT_BODY on Gen10 use arrays Signed-off-by: Anuj Phogat <[email protected]> Tested-by: Anuj Phogat <[email protected]>
* i965: Make feature macros gen8 basedBen Widawsky2017-06-091-8/+5
| | | | | | | | | | All the "features" of the hardware are similar starting with GEN8, so remove as much of the GEN9 uniqueness as possible. This makes implementing future gen platforms a bit easier. Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/isl: Add an enum for describing auxiliary compression stateJason Ekstrand2017-06-071-0/+169
| | | | | | | | | | | | This enum describes all of the states that a auxiliary compressed surface can have. All of the states as well as normative language for referring to each of the compression operations is provided in the truly colossal comment for the new isl_aux_state enum. There is also a diagram showing how surfaces move between the different states. Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Nanley Chery <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* blorp: Use FullSurfaceDepthandStencilClear for blorp_hiz_opJason Ekstrand2017-06-073-0/+5
| | | | | | | The blorp_hiz_op entrypoint always acts on a full subresource of a HiZ buffer so we can just set the flag unconditionally. Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/blorp: Plumb through access to the workaround BOJason Ekstrand2017-06-072-2/+19
| | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101283 Reviewed-by: Topi Pohjolainen <[email protected]>
* anv/blorp: Move the depth cache flush outside of BLORPNanley Chery2017-06-072-8/+16
| | | | | Signed-off-by: Nanley Chery <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/blorp: Refactor the HiZ op interfaceJason Ekstrand2017-06-073-53/+59
| | | | | | | | | | This commit does a few things: 1) Now that BLORP can do HiZ ops on gen8+, drop the gen6 prefix. 2) Switch parameters to uint32_t to match the rest of blorp. 3) Take a range of layers and loop internally. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/miptree: Store fast clear colors in an isl_color_valueJason Ekstrand2017-06-073-2/+21
| | | | | | | | | | | | | | | | | | | | | | | | This commit, out of necessity, makes a number of changes at once: 1) Changes intel_mipmap_tree to store the clear color for both color and depth as an isl_color_value. 2) Changes the depth/stencil emit code to do the format conversion of the depth clear value on Haswell and earlier instead of pulling a uint32_t directly from the miptree. 3) Changes ISL's depth/stencil emit code to perform the format conversion of the depth clear value on Haswell and earlier instead of assuming that the depth value in the float is pre-converted. 4) Changes blorp to pass the depth value through as a float. 5) Changes the Vulkan driver to pass the depth value to blorp as a float rather than a uint. Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* intel: Fix broxton 2x6 way size computationAnuj Phogat2017-06-061-0/+4
| | | | | | | | | | | | | | | | | This patch is undoing the changes to way size computation in broxton 2x6, made by below commit: Commit: 0d576fbfbe912cf3fb9ab594bb31eb58bccf2138 Author: Anuj Phogat <[email protected]> i965: Simplify l3 way size computations By making use of l3_banks field in gen_device_info struct l3_way_size for gen7+ = 2 * l3_banks. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101306 Signed-off-by: Anuj Phogat <[email protected]> Tested-by: Mark Janes <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* tree-wide: remove trailing backslashEric Engestrom2017-06-071-1/+1
| | | | | | | | | Simple search for a backslash followed by two newlines. If one of the newlines were to be removed, this would cause issues, so let's just remove these trailing backslashes. Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* anv: Set better descriptor set limitsAlex Smith2017-06-061-3/+6
| | | | | | | | | | | | | Based on discussions with Jason, Ivy Bridge and Bay Trail only actually support 16 samplers, while newer hardware can support more than the current limit of 64. Therefore set the lower limit where needed, and bump up to 128 for everything else. There is also a limit on the total number of other resources of around 250. This allows Dawn of War III to render correctly on ANV. Signed-off-by: Alex Smith <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* anv: Set driver version to Mesa versionAlex Smith2017-06-061-1/+1
| | | | | | | | | | | | As already done by RADV. v2: Move version calculation function to src/vulkan/util to share with RADV. Signed-off-by: Alex Smith <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* util/vulkan: Move Vulkan utilities to src/vulkan/utilAlex Smith2017-06-068-8/+8
| | | | | | | | | | | | | We have Vulkan utilities in both src/util and src/vulkan/util. The latter seems a more appropriate place for Vulkan-specific things, so move them there. v2: Android build system changes (from Tapani Pälli) Signed-off-by: Alex Smith <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> Acked-by: Jason Ekstrand <[email protected]>
* intel: gen-decoder: rework how we handle groupsLionel Landwerlin2017-06-063-104/+161
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current way of handling groups doesn't seem to be able to handle MI_LOAD_REGISTER_* with more than one register. This change reworks the way we handle groups by building a traversal list on loading the GENXML files. Let's say you have Instruction { Field0 Field1 Field2 Group0 (count=2) { Field0-0 Field0-1 } Group1 (count=4) { Field1-0 Field1-1 } } We build of linked on load that goes : Instruction -> Group0 -> Group1 All of those are gen_group structures, making the traversal trivial. We just need to iterate groups for the right number of timers (count field in genxml). The more fancy case is when you have only a single group of unknown size (count=0). In that case we keep on reading that group for as long as we're within the DWordLength of that instruction. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]>
* i965: Change INTEL_DEBUG=vec4 to INTEL_SCALAR_VS for consistency.Kenneth Graunke2017-06-053-3/+2
| | | | | | | | | We moved to INTEL_SCALAR_* when we added more than a single stage, but never went back and converted the VS to work that way. Be consistent. Also update the documentation to actually mention these debug variables. Acked-by: Jason Ekstrand <[email protected]>
* i965: Simplify l3 way size computationsAnuj Phogat2017-06-021-10/+2
| | | | | | | | | | | By making use of l3_banks field in gen_device_info struct l3_way_size for gen7+ = 2 * l3_banks. V2: Keep the get_l3_way_size() function. Suggested-by: Francisco Jerez <[email protected]> Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* i965: Add and initialize l3_banks field for gen7+Anuj Phogat2017-06-022-3/+27
| | | | | | | | | | | This new field helps simplify l3 way size computations in next patch. V2: Initialize the l3_banks to 0 in macros. Suggested-by: Francisco Jerez <[email protected]> Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* intel/blorp: Handle gen6 stencil/HiZ offsets in the back-endJason Ekstrand2017-06-011-2/+30
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/isl: Add a helper for getting the byte/tile offset of a subimageJason Ekstrand2017-06-013-9/+64
| | | | | | | | | Frequently, get_image_offset_sa is combined with get_intratile_offset_sa so it makes sense to have a single helper to do both. If the caller doesn't want the intratile offsets, it can simply pass NULL and ISL will assert that they are 0. Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/isl: Make get_intratile_offset_el take the element size in bitsJason Ekstrand2017-06-012-8/+5
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/isl: Add a new layout for HiZ and stencil on Sandy BridgeJason Ekstrand2017-06-012-5/+197
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/isl: Generate phys_total_el from isl_calc_phys_extentJason Ekstrand2017-06-011-68/+97
| | | | | | | | | | The only surface layout for which slice0 makes any sense is GEN4_2D. Move all of the slice0 stuff into isl_calc_phys_total_extent_el_gen4_2d and make the others trivially return the total size in surface elements. As a side-effect, array_pitch_el_rows is now returned from these helpers as well. Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/isl: Don't check array pitch for gen4 3D texturesJason Ekstrand2017-06-011-1/+0
| | | | | | Array pitch doesn't matter in this layout. Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/isl: Refactor to use a phys_total_el extent.Jason Ekstrand2017-06-011-19/+19
| | | | | | | We've already implicitly been using a physical total size in surface elements. This just centralizes things a bit. Reviewed-by: Topi Pohjolainen <[email protected]>
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