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* i965/fs: retype offset_reg to UD at load_ssboJose Maria Casanova Crespo2018-04-201-1/+1
* nir: Offset vertex_id by first_vertex instead of base_vertexNeil Roberts2018-04-192-7/+1
* spirv: Lower BaseVertex to FIRST_VERTEX instead of BASE_VERTEXNeil Roberts2018-04-192-4/+14
* intel: Handle firstvertex in an identical way to BaseVertexAntia Puentes2018-04-193-0/+8
* intel/compiler: Add a uses_firstvertex flagNeil Roberts2018-04-192-0/+5
* anv,radv: Drop XML workarounds for VK_ANDROID_native_bufferJason Ekstrand2018-04-161-6/+1
* anv: fix number of planes for depth & stencilLionel Landwerlin2018-04-132-1/+5
* mesa: include mtypes.h lessMarek Olšák2018-04-123-0/+3
* blorp: Silence unused function warningsNanley Chery2018-04-112-3/+3
* vulkan: fix build issue on android (both anv/radv)Tapani Pälli2018-04-111-2/+2
* vulkan: Drop vk_android_native_buffer.xmlJason Ekstrand2018-04-104-32/+16
* intel/dev: Assert the number of slices is not zeroTopi Pohjolainen2018-04-111-1/+1
* anv/pipeline: Lower more constant initializers earlierJason Ekstrand2018-04-091-7/+5
* intel: aubinator: print out addresses of invalid instructionsLionel Landwerlin2018-04-101-9/+14
* intel/compiler: Explicitly cast register type in switchIan Romanick2018-04-061-1/+1
* anv: Add WSI support for the I915_FORMAT_MOD_Y_TILED_CCSJason Ekstrand2018-04-052-19/+40
* intel/tools: new intel_sanitize_gpu toolKevin Rogovin2018-04-053-0/+459
* anv: Make blorp update the clear color.Rafael Antognolli2018-04-053-63/+66
* anv: Use clear address for HiZ fast clears too.Rafael Antognolli2018-04-053-3/+27
* anv: Emit the fast clear color address, instead of value.Rafael Antognolli2018-04-053-4/+70
* anv: Add a helper to extract clear color from the attachment.Rafael Antognolli2018-04-052-13/+21
* intel/blorp: Update clear color state buffer during fast clears.Rafael Antognolli2018-04-051-0/+48
* intel/blorp: Only copy clear color when doing a resolve.Rafael Antognolli2018-04-051-4/+9
* intel/blorp: Add support for fast clear address.Rafael Antognolli2018-04-051-5/+13
* intel/isl: Add support to emit clear value address.Rafael Antognolli2018-04-052-4/+23
* intel: Use Clear Color struct size.Rafael Antognolli2018-04-056-15/+35
* intel/genxml: Add Clear Color struct to gen10+.Rafael Antognolli2018-04-052-0/+18
* intel/genxml: Use a single field for clear color address on gen10.Rafael Antognolli2018-04-052-8/+6
* genxml: Preserve fields that share dword space with addresses.Rafael Antognolli2018-04-051-2/+6
* anv/image: Do not override lower bits of dword.Rafael Antognolli2018-04-052-15/+12
* intel: compiler: silence compiler warningLionel Landwerlin2018-04-041-0/+1
* anv: Fix close(fd) before import issue in vkCreateDmaBufImageINTELKevin Strasser2018-04-031-2/+2
* intel: gen-decoder: print all dword a field belongs toLionel Landwerlin2018-04-032-7/+9
* intel: genxml: decode variable length MI_LRILionel Landwerlin2018-04-0310-0/+40
* intel: gen-decoder: don't decode fields beyond a dword lengthLionel Landwerlin2018-04-031-15/+26
* intel: error_decode: add an option to decode all buffersLionel Landwerlin2018-04-031-2/+7
* intel: genxml: add preemption control instructionsLionel Landwerlin2018-04-034-0/+26
* nir+drivers: add helpers to get # of src/dest componentsRob Clark2018-04-031-6/+5
* anv/cmd_buffer: honor pending clear views for depth/stencil attachmentsIago Toral Quiroga2018-04-021-1/+21
* anv/cmd_buffer: consider multiview masks for tracking pending clear aspectsIago Toral Quiroga2018-04-022-3/+96
* intel/vec4: Set channel_sizes for MOV_INDIRECT sourcesJason Ekstrand2018-03-301-1/+4
* util: Add and use util_is_power_of_two_nonzeroIan Romanick2018-03-291-2/+2
* util: Move util_is_power_of_two to bitscan.h and rename to util_is_power_of_t...Ian Romanick2018-03-294-8/+8
* autotools: Include intel/dev/meson.build in tarballDylan Baker2018-03-281-0/+1
* intel/fs: Don't emit a des copy for image ops with has_dest == falseJason Ekstrand2018-03-271-3/+6
* intel/aubinator_error_decode: Decode more registers.Rafael Antognolli2018-03-261-0/+12
* intel/genxml: Add SAMPLER_INSTDONE register.Rafael Antognolli2018-03-266-0/+139
* intel/genxml: Add ROW_INSTDONE register.Rafael Antognolli2018-03-266-0/+114
* intel/genxml: Add SC_INSTDONE register.Rafael Antognolli2018-03-266-0/+140
* i965/vec4: Fix null destination register in 3-source instructionsIan Romanick2018-03-262-0/+27
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